// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.8.0.115.3
// Netlist written on Tue Jun 13 21:45:51 2017
//
// Verilog Description of module Pulse_gen
//

module Pulse_gen (clk_in, rst_n_in, key_menu, key_up, key_down, menu_state, 
            pulse_out, led_misc, b_led) /* synthesis syn_module_defined=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(1[8:17])
    input clk_in;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(3[11:17])
    input rst_n_in;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(4[11:19])
    input key_menu;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(5[11:19])
    input key_up;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(6[11:17])
    input key_down;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(7[11:19])
    output menu_state;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(8[12:22])
    output [1:0]pulse_out;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(9[20:29])
    output [15:0]led_misc;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(11[19:27])
    output [0:0]b_led;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(12[18:23])
    
    wire clk_in_c /* synthesis SET_AS_NETWORK=clk_in_c, is_clock=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(3[11:17])
    wire [1:0]div_clko /* synthesis SET_AS_NETWORK=div_clko[0], is_clock=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(19[12:20])
    wire clk_N_161 /* synthesis is_inv_clock=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(55[26:31])
    
    wire GND_net, VCC_net, rst_n_in_c, key_menu_c, key_up_c, key_down_c, 
        pulse_out_c, led_misc_c, b_led_c_0, menu_state_c_2;
    wire [3:0]cycle;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(69[11:16])
    wire [3:0]duty;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(70[11:15])
    wire [3:0]cnt;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(89[11:14])
    
    wire n13, n49, n50, n799, n4, cnt_3__N_29;
    wire [1:0]pulse_out_1__N_1;
    wire [12:0]cnt2;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(40[12:16])
    
    wire n6;
    wire [31:0]breath_led_N_88;
    
    wire breath_led_N_87, n312, n4_adj_270, n1442, n4_adj_271, n1443, 
        rst_n_N_222, clk_in_c_enable_8, n6_adj_272, n6_adj_273, n4_adj_274, 
        n6_adj_275, n1840, n615, n1448, n1444, n1901, n1544, n1900, 
        n1767, n1763, n6_adj_276, n6_adj_277, n1446, n1445, n1447, 
        n1759, n1899, n1546, n1894, n1545, n1893, n1892, n1547, 
        n2017, n22, n23, n24, n25;
    
    VHI i1516 (.Z(VCC_net));
    INV i1518 (.A(clk_in_c), .Z(clk_N_161));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(3[11:17])
    FD1S3AY pulse_out_i1 (.D(pulse_out_1__N_1[1]), .CK(clk_in_c), .Q(pulse_out_c));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(109[11] 116[5])
    defparam pulse_out_i1.GSR = "ENABLED";
    OB led_misc_pad_12 (.I(led_misc_c), .O(led_misc[12]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(11[19:27])
    FD1S3AX led_misc_i1 (.D(n2017), .CK(clk_in_c), .Q(led_misc_c));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(125[11] 128[5])
    defparam led_misc_i1.GSR = "ENABLED";
    OB led_misc_pad_13 (.I(led_misc_c), .O(led_misc[13]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(11[19:27])
    FD1S3AY b_led_0__49 (.D(breath_led_N_87), .CK(clk_in_c), .Q(b_led_c_0));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(125[11] 128[5])
    defparam b_led_0__49.GSR = "ENABLED";
    OB led_misc_pad_14 (.I(led_misc_c), .O(led_misc[14]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(11[19:27])
    OB led_misc_pad_15 (.I(led_misc_c), .O(led_misc[15]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(11[19:27])
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    OB pulse_out_pad_0 (.I(pulse_out_c), .O(pulse_out[0]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(9[20:29])
    LUT4 i2_3_lut (.A(n4_adj_271), .B(n13), .C(cycle[2]), .Z(n1544)) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(B (C)+!B !(C)))) */ ;
    defparam i2_3_lut.init = 16'h6969;
    OB pulse_out_pad_1 (.I(pulse_out_c), .O(pulse_out[1]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(9[20:29])
    OB menu_state_pad (.I(menu_state_c_2), .O(menu_state));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(8[12:22])
    LUT4 i2_4_lut (.A(cycle[0]), .B(n13), .C(n799), .D(cycle[1]), .Z(n1545)) /* synthesis lut_function=(!(A (B (D)+!B !(D))+!A !(B (D)+!B !(C (D)+!C !(D))))) */ ;
    defparam i2_4_lut.init = 16'h6798;
    LUT4 i1187_1_lut (.A(cnt[0]), .Z(n25)) /* synthesis lut_function=(!(A)) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(99[15:25])
    defparam i1187_1_lut.init = 16'h5555;
    LUT4 i1189_2_lut (.A(cnt[1]), .B(cnt[0]), .Z(n24)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(99[15:25])
    defparam i1189_2_lut.init = 16'h6666;
    FD1P3AX duty_i0_i0 (.D(n615), .SP(clk_in_c_enable_8), .CK(clk_in_c), 
            .Q(duty[0]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(76[11] 86[5])
    defparam duty_i0_i0.GSR = "ENABLED";
    LUT4 mux_116_i4_4_lut (.A(duty[3]), .B(n1892), .C(n50), .D(n6), 
         .Z(n312)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(81[12] 85[6])
    defparam mux_116_i4_4_lut.init = 16'hcac5;
    FD1P3AX cycle_i0_i0 (.D(n1547), .SP(menu_state_c_2), .CK(clk_in_c), 
            .Q(cycle[0]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(76[11] 86[5])
    defparam cycle_i0_i0.GSR = "ENABLED";
    PFUMX LessThan_15_i8 (.BLUT(n4_adj_274), .ALUT(n6_adj_272), .C0(n1759), 
          .Z(n49));
    PFUMX cycle_3__I_0_i8 (.BLUT(n4), .ALUT(n6_adj_273), .C0(n1767), .Z(cnt_3__N_29));
    PFUMX cnt_3__I_0_i8 (.BLUT(n4_adj_270), .ALUT(n6_adj_275), .C0(n1763), 
          .Z(pulse_out_1__N_1[1]));
    LUT4 i2_4_lut_adj_18 (.A(cycle[2]), .B(n13), .C(cycle[3]), .D(n4_adj_271), 
         .Z(n1546)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(B (C)+!B (C (D)+!C !(D))))) */ ;
    defparam i2_4_lut_adj_18.init = 16'h78e1;
    LUT4 i235_4_lut (.A(cycle[1]), .B(n13), .C(n799), .D(cycle[0]), 
         .Z(n4_adj_271)) /* synthesis lut_function=(A ((D)+!B)+!A !(B+!((D)+!C))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(81[12] 85[6])
    defparam i235_4_lut.init = 16'hbb23;
    FD1S3IX cnt_171__i0 (.D(n25), .CK(div_clko[0]), .CD(cnt_3__N_29), 
            .Q(cnt[0]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(99[15:25])
    defparam cnt_171__i0.GSR = "ENABLED";
    FD1S3IX cnt_171__i3 (.D(n22), .CK(div_clko[0]), .CD(cnt_3__N_29), 
            .Q(cnt[3]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(99[15:25])
    defparam cnt_171__i3.GSR = "ENABLED";
    OB led_misc_pad_11 (.I(led_misc_c), .O(led_misc[11]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(11[19:27])
    LUT4 mux_116_i3_4_lut_4_lut_then_4_lut (.A(duty[0]), .B(duty[1]), .C(n1894), 
         .D(n50), .Z(n1900)) /* synthesis lut_function=(!(A (B (D))+!A !(B+((D)+!C)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(82[48:59])
    defparam mux_116_i3_4_lut_4_lut_then_4_lut.init = 16'h77ef;
    LUT4 i1203_3_lut_4_lut (.A(cnt[1]), .B(cnt[0]), .C(cnt[2]), .D(cnt[3]), 
         .Z(n22)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(99[15:25])
    defparam i1203_3_lut_4_lut.init = 16'h7f80;
    CCU2D sub_139_add_2_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(breath_led_N_88[0]), .B1(cnt2[0]), .C1(GND_net), .D1(GND_net), 
          .COUT(n1442));
    defparam sub_139_add_2_1.INIT0 = 16'h0000;
    defparam sub_139_add_2_1.INIT1 = 16'h5999;
    defparam sub_139_add_2_1.INJECT1_0 = "NO";
    defparam sub_139_add_2_1.INJECT1_1 = "NO";
    LUT4 mux_116_i1_3_lut (.A(duty[0]), .B(n50), .C(n1894), .Z(n615)) /* synthesis lut_function=(!(A (B+(C))+!A !(B+(C)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(81[12] 85[6])
    defparam mux_116_i1_3_lut.init = 16'h5656;
    LUT4 mux_116_i3_4_lut_4_lut_else_4_lut (.A(duty[0]), .B(duty[1]), .C(n1894), 
         .D(n50), .Z(n1899)) /* synthesis lut_function=(A (B (D))+!A !(B+((D)+!C))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(82[48:59])
    defparam mux_116_i3_4_lut_4_lut_else_4_lut.init = 16'h8810;
    LUT4 i2_2_lut (.A(duty[3]), .B(duty[1]), .Z(n6_adj_276)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i2_2_lut.init = 16'heeee;
    LUT4 i271_2_lut_3_lut_4_lut (.A(duty[0]), .B(n1894), .C(duty[2]), 
         .D(duty[1]), .Z(n6)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(83[47:58])
    defparam i271_2_lut_3_lut_4_lut.init = 16'hfffb;
    LUT4 i1196_2_lut_3_lut (.A(cnt[1]), .B(cnt[0]), .C(cnt[2]), .Z(n23)) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(99[15:25])
    defparam i1196_2_lut_3_lut.init = 16'h7878;
    LUT4 cnt_3__I_0_i6_3_lut_3_lut (.A(cnt[3]), .B(duty[3]), .C(duty[2]), 
         .Z(n6_adj_275)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(111[6:15])
    defparam cnt_3__I_0_i6_3_lut_3_lut.init = 16'hd4d4;
    GSR GSR_INST (.GSR(rst_n_in_c));
    FD1S3IX cnt_171__i2 (.D(n23), .CK(div_clko[0]), .CD(cnt_3__N_29), 
            .Q(cnt[2]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(99[15:25])
    defparam cnt_171__i2.GSR = "ENABLED";
    FD1S3IX cnt_171__i1 (.D(n24), .CK(div_clko[0]), .CD(cnt_3__N_29), 
            .Q(cnt[1]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(99[15:25])
    defparam cnt_171__i1.GSR = "ENABLED";
    LUT4 LessThan_15_i6_3_lut_3_lut (.A(n1892), .B(cycle[3]), .C(cycle[2]), 
         .Z(n6_adj_272)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(82[19:38])
    defparam LessThan_15_i6_3_lut_3_lut.init = 16'hd4d4;
    CCU2D sub_139_add_2_9 (.A0(breath_led_N_88[7]), .B0(cnt2[7]), .C0(GND_net), 
          .D0(GND_net), .A1(breath_led_N_88[8]), .B1(cnt2[8]), .C1(GND_net), 
          .D1(GND_net), .CIN(n1445), .COUT(n1446));
    defparam sub_139_add_2_9.INIT0 = 16'h5999;
    defparam sub_139_add_2_9.INIT1 = 16'h5999;
    defparam sub_139_add_2_9.INJECT1_0 = "NO";
    defparam sub_139_add_2_9.INJECT1_1 = "NO";
    LUT4 i2_3_lut_adj_19 (.A(n13), .B(n799), .C(cycle[0]), .Z(n1547)) /* synthesis lut_function=(!(A (C)+!A (B (C)+!B !(C)))) */ ;
    defparam i2_3_lut_adj_19.init = 16'h1e1e;
    CCU2D sub_139_add_2_11 (.A0(breath_led_N_88[9]), .B0(cnt2[9]), .C0(GND_net), 
          .D0(GND_net), .A1(breath_led_N_88[10]), .B1(cnt2[10]), .C1(GND_net), 
          .D1(GND_net), .CIN(n1446), .COUT(n1447));
    defparam sub_139_add_2_11.INIT0 = 16'h5999;
    defparam sub_139_add_2_11.INIT1 = 16'h5999;
    defparam sub_139_add_2_11.INJECT1_0 = "NO";
    defparam sub_139_add_2_11.INJECT1_1 = "NO";
    CCU2D sub_139_add_2_7 (.A0(breath_led_N_88[5]), .B0(cnt2[5]), .C0(GND_net), 
          .D0(GND_net), .A1(breath_led_N_88[6]), .B1(cnt2[6]), .C1(GND_net), 
          .D1(GND_net), .CIN(n1444), .COUT(n1445));
    defparam sub_139_add_2_7.INIT0 = 16'h5999;
    defparam sub_139_add_2_7.INIT1 = 16'h5999;
    defparam sub_139_add_2_7.INJECT1_0 = "NO";
    defparam sub_139_add_2_7.INJECT1_1 = "NO";
    LUT4 i2_2_lut_adj_20 (.A(cycle[1]), .B(cycle[3]), .Z(n6_adj_277)) /* synthesis lut_function=(A (B)) */ ;
    defparam i2_2_lut_adj_20.init = 16'h8888;
    LUT4 i1483_3_lut_4_lut (.A(cnt[3]), .B(duty[3]), .C(duty[2]), .D(cnt[2]), 
         .Z(n1763)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D))))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(111[6:15])
    defparam i1483_3_lut_4_lut.init = 16'h6ff6;
    TSALL TSALL_INST (.TSALL(GND_net));
    LUT4 duty_1__bdd_4_lut (.A(duty[1]), .B(n1894), .C(n50), .D(duty[0]), 
         .Z(n1840)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B (C (D)))+!A !(B (C (D)+!C !(D))+!B (C (D))))) */ ;
    defparam duty_1__bdd_4_lut.init = 16'h5aa6;
    CCU2D sub_139_add_2_3 (.A0(breath_led_N_88[1]), .B0(cnt2[1]), .C0(GND_net), 
          .D0(GND_net), .A1(breath_led_N_88[2]), .B1(cnt2[2]), .C1(GND_net), 
          .D1(GND_net), .CIN(n1442), .COUT(n1443));
    defparam sub_139_add_2_3.INIT0 = 16'h5999;
    defparam sub_139_add_2_3.INIT1 = 16'h5999;
    defparam sub_139_add_2_3.INJECT1_0 = "NO";
    defparam sub_139_add_2_3.INJECT1_1 = "NO";
    FD1P3AX duty_i0_i3 (.D(n312), .SP(clk_in_c_enable_8), .CK(clk_in_c), 
            .Q(duty[3]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(76[11] 86[5])
    defparam duty_i0_i3.GSR = "ENABLED";
    FD1P3AY duty_i0_i2 (.D(n1901), .SP(clk_in_c_enable_8), .CK(clk_in_c), 
            .Q(duty[2]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(76[11] 86[5])
    defparam duty_i0_i2.GSR = "ENABLED";
    FD1P3AX duty_i0_i1 (.D(n1840), .SP(clk_in_c_enable_8), .CK(clk_in_c), 
            .Q(duty[1]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(76[11] 86[5])
    defparam duty_i0_i1.GSR = "ENABLED";
    CCU2D sub_139_add_2_cout (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1448), .S0(breath_led_N_87));
    defparam sub_139_add_2_cout.INIT0 = 16'h0000;
    defparam sub_139_add_2_cout.INIT1 = 16'h0000;
    defparam sub_139_add_2_cout.INJECT1_0 = "NO";
    defparam sub_139_add_2_cout.INJECT1_1 = "NO";
    VLO i1 (.Z(GND_net));
    CCU2D sub_139_add_2_5 (.A0(breath_led_N_88[3]), .B0(cnt2[3]), .C0(GND_net), 
          .D0(GND_net), .A1(breath_led_N_88[4]), .B1(cnt2[4]), .C1(GND_net), 
          .D1(GND_net), .CIN(n1443), .COUT(n1444));
    defparam sub_139_add_2_5.INIT0 = 16'h5999;
    defparam sub_139_add_2_5.INIT1 = 16'h5999;
    defparam sub_139_add_2_5.INJECT1_0 = "NO";
    defparam sub_139_add_2_5.INJECT1_1 = "NO";
    CCU2D sub_139_add_2_13 (.A0(breath_led_N_88[11]), .B0(cnt2[11]), .C0(GND_net), 
          .D0(GND_net), .A1(breath_led_N_88[12]), .B1(cnt2[12]), .C1(GND_net), 
          .D1(GND_net), .CIN(n1447), .COUT(n1448));
    defparam sub_139_add_2_13.INIT0 = 16'h5999;
    defparam sub_139_add_2_13.INIT1 = 16'h5999;
    defparam sub_139_add_2_13.INJECT1_0 = "NO";
    defparam sub_139_add_2_13.INJECT1_1 = "NO";
    Debounce_U1 Debounce_uut0 (.GND_net(GND_net), .clk_in_c(clk_in_c), .key_down_c(key_down_c), 
            .n49(n49), .n799(n799), .rst_n_in_c(rst_n_in_c), .rst_n_N_222(rst_n_N_222), 
            .\duty[0] (duty[0]), .n6(n6_adj_276), .\duty[2] (duty[2]), 
            .n1894(n1894)) /* synthesis syn_module_defined=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(55[10] 62[2])
    FD1P3AY cycle_i0_i3 (.D(n1546), .SP(menu_state_c_2), .CK(clk_in_c), 
            .Q(cycle[3]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(76[11] 86[5])
    defparam cycle_i0_i3.GSR = "ENABLED";
    FD1P3AX cycle_i0_i2 (.D(n1544), .SP(menu_state_c_2), .CK(clk_in_c), 
            .Q(cycle[2]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(76[11] 86[5])
    defparam cycle_i0_i2.GSR = "ENABLED";
    FD1P3AX cycle_i0_i1 (.D(n1545), .SP(menu_state_c_2), .CK(clk_in_c), 
            .Q(cycle[1]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(76[11] 86[5])
    defparam cycle_i0_i1.GSR = "ENABLED";
    OB led_misc_pad_10 (.I(led_misc_c), .O(led_misc[10]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(11[19:27])
    OB led_misc_pad_9 (.I(led_misc_c), .O(led_misc[9]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(11[19:27])
    OB led_misc_pad_8 (.I(led_misc_c), .O(led_misc[8]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(11[19:27])
    OB led_misc_pad_7 (.I(led_misc_c), .O(led_misc[7]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(11[19:27])
    OB led_misc_pad_6 (.I(led_misc_c), .O(led_misc[6]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(11[19:27])
    OB led_misc_pad_5 (.I(led_misc_c), .O(led_misc[5]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(11[19:27])
    OB led_misc_pad_4 (.I(led_misc_c), .O(led_misc[4]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(11[19:27])
    OB led_misc_pad_3 (.I(led_misc_c), .O(led_misc[3]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(11[19:27])
    OB led_misc_pad_2 (.I(led_misc_c), .O(led_misc[2]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(11[19:27])
    OB led_misc_pad_1 (.I(led_misc_c), .O(led_misc[1]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(11[19:27])
    OB led_misc_pad_0 (.I(led_misc_c), .O(led_misc[0]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(11[19:27])
    OB b_led_pad_0 (.I(b_led_c_0), .O(b_led[0]));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(12[18:23])
    IB clk_in_pad (.I(clk_in), .O(clk_in_c));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(3[11:17])
    IB rst_n_in_pad (.I(rst_n_in), .O(rst_n_in_c));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(4[11:19])
    IB key_menu_pad (.I(key_menu), .O(key_menu_c));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(5[11:19])
    IB key_up_pad (.I(key_up), .O(key_up_c));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(6[11:17])
    IB key_down_pad (.I(key_down), .O(key_down_c));   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(7[11:19])
    breath_led breath_instance1 (.cnt2({cnt2}), .clk_in_c(clk_in_c), .GND_net(GND_net), 
            .\breath_led_N_88[3] (breath_led_N_88[3]), .\breath_led_N_88[4] (breath_led_N_88[4]), 
            .\breath_led_N_88[0] (breath_led_N_88[0]), .\breath_led_N_88[2] (breath_led_N_88[2]), 
            .\breath_led_N_88[1] (breath_led_N_88[1]), .\breath_led_N_88[11] (breath_led_N_88[11]), 
            .\breath_led_N_88[12] (breath_led_N_88[12]), .\breath_led_N_88[9] (breath_led_N_88[9]), 
            .\breath_led_N_88[10] (breath_led_N_88[10]), .\breath_led_N_88[7] (breath_led_N_88[7]), 
            .\breath_led_N_88[8] (breath_led_N_88[8]), .\breath_led_N_88[5] (breath_led_N_88[5]), 
            .\breath_led_N_88[6] (breath_led_N_88[6])) /* synthesis syn_module_defined=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(22[12] 27[2])
    LUT4 cycle_3__I_0_i6_3_lut_3_lut (.A(cycle[3]), .B(cnt[3]), .C(cnt[2]), 
         .Z(n6_adj_273)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(95[6:16])
    defparam cycle_3__I_0_i6_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i1482_3_lut_4_lut (.A(cycle[3]), .B(cnt[3]), .C(cnt[2]), .D(cycle[2]), 
         .Z(n1767)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D))))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(95[6:16])
    defparam i1482_3_lut_4_lut.init = 16'h6ff6;
    LUT4 i1484_3_lut_4_lut (.A(n1892), .B(cycle[3]), .C(cycle[2]), .D(n1893), 
         .Z(n1759)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D))))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(82[19:38])
    defparam i1484_3_lut_4_lut.init = 16'h6ff6;
    LUT4 LessThan_15_i4_4_lut_4_lut (.A(duty[1]), .B(duty[0]), .C(cycle[1]), 
         .D(cycle[0]), .Z(n4_adj_274)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C (D))+!B (C))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(82[48:59])
    defparam LessThan_15_i4_4_lut_4_lut.init = 16'hd890;
    divide divide_uut1 (.GND_net(GND_net), .clk_in_c(clk_in_c), .rst_n_N_222(rst_n_N_222), 
           .\div_clko[0] (div_clko[0]), .clk_N_161(clk_N_161), .rst_n_in_c(rst_n_in_c)) /* synthesis syn_module_defined=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(31[8] 35[2])
    PFUMX i1498 (.BLUT(n1899), .ALUT(n1900), .C0(duty[2]), .Z(n1901));
    LUT4 m1_lut (.Z(n2017)) /* synthesis lut_function=1, syn_instantiated=1 */ ;
    defparam m1_lut.init = 16'hffff;
    LUT4 cycle_3__I_0_i4_4_lut (.A(cnt[0]), .B(cnt[1]), .C(cycle[1]), 
         .D(cycle[0]), .Z(n4)) /* synthesis lut_function=(A (B+!(C))+!A !(B (C (D))+!B (C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(95[6:16])
    defparam cycle_3__I_0_i4_4_lut.init = 16'h8ecf;
    LUT4 cnt_3__I_0_i4_4_lut (.A(duty[0]), .B(duty[1]), .C(cnt[1]), .D(cnt[0]), 
         .Z(n4_adj_270)) /* synthesis lut_function=(A (B+!(C))+!A !(B (C (D))+!B (C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(111[6:15])
    defparam cnt_3__I_0_i4_4_lut.init = 16'h8ecf;
    Debounce Debounce_uut2 (.clk_in_c(clk_in_c), .key_menu_c(key_menu_c), 
            .menu_state_c_2(menu_state_c_2), .GND_net(GND_net), .clk_in_c_enable_8(clk_in_c_enable_8)) /* synthesis syn_module_defined=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(37[10] 44[2])
    LUT4 i216_3_lut_rep_9_4_lut (.A(duty[1]), .B(duty[0]), .C(duty[2]), 
         .D(duty[3]), .Z(n1892)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(82[48:59])
    defparam i216_3_lut_rep_9_4_lut.init = 16'h7f80;
    LUT4 i209_2_lut_rep_10_3_lut (.A(duty[1]), .B(duty[0]), .C(duty[2]), 
         .Z(n1893)) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(82[48:59])
    defparam i209_2_lut_rep_10_3_lut.init = 16'h7878;
    Debounce_U0 Debounce_uut1 (.clk_in_c(clk_in_c), .key_up_c(key_up_c), 
            .GND_net(GND_net), .n49(n49), .n50(n50), .\cycle[0] (cycle[0]), 
            .n6(n6_adj_277), .\cycle[2] (cycle[2]), .n13(n13)) /* synthesis syn_module_defined=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(46[10] 53[2])
    
endmodule
//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

//
// Verilog Description of module TSALL
// module not written out since it is a black-box. 
//

//
// Verilog Description of module Debounce_U1
//

module Debounce_U1 (GND_net, clk_in_c, key_down_c, n49, n799, rst_n_in_c, 
            rst_n_N_222, \duty[0] , n6, \duty[2] , n1894) /* synthesis syn_module_defined=1 */ ;
    input GND_net;
    input clk_in_c;
    input key_down_c;
    input n49;
    output n799;
    input rst_n_in_c;
    output rst_n_N_222;
    input \duty[0] ;
    input n6;
    input \duty[2] ;
    output n1894;
    
    wire clk_in_c /* synthesis SET_AS_NETWORK=clk_in_c, is_clock=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(3[11:17])
    wire [18:0]cnt;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(18[12:15])
    wire [18:0]n81;
    
    wire n1474, low_sw_r, low_sw, key_rst, clk_in_c_enable_5, key_an, 
        n1898, n1571, n12, n8, n22, n18, n20, n14, n1482, 
        n1481, n1480, n1479, n1478, n1477, n1476, n1475;
    
    CCU2D cnt_178_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n1474), 
          .S1(n81[0]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178_add_4_1.INIT0 = 16'hF000;
    defparam cnt_178_add_4_1.INIT1 = 16'h0555;
    defparam cnt_178_add_4_1.INJECT1_0 = "NO";
    defparam cnt_178_add_4_1.INJECT1_1 = "NO";
    FD1S3AY low_sw_r_34 (.D(low_sw), .CK(clk_in_c), .Q(low_sw_r)) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=10, LSE_RCOL=2, LSE_LLINE=55, LSE_RLINE=62 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(36[11:30])
    defparam low_sw_r_34.GSR = "ENABLED";
    FD1S3AY key_rst_31 (.D(key_down_c), .CK(clk_in_c), .Q(key_rst)) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=10, LSE_RCOL=2, LSE_LLINE=55, LSE_RLINE=62 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(13[11:27])
    defparam key_rst_31.GSR = "ENABLED";
    FD1P3AY low_sw_33 (.D(key_down_c), .SP(clk_in_c_enable_5), .CK(clk_in_c), 
            .Q(low_sw));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[7] 30[25])
    defparam low_sw_33.GSR = "ENABLED";
    FD1S3IX cnt_178__i0 (.D(n81[0]), .CK(clk_in_c), .CD(key_an), .Q(cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i0.GSR = "ENABLED";
    LUT4 i1_2_lut_rep_15 (.A(low_sw), .B(low_sw_r), .Z(n1898)) /* synthesis lut_function=(!(A+!(B))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(40[19:40])
    defparam i1_2_lut_rep_15.init = 16'h4444;
    LUT4 i1_2_lut_3_lut (.A(low_sw), .B(low_sw_r), .C(n49), .Z(n799)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(40[19:40])
    defparam i1_2_lut_3_lut.init = 16'h4040;
    LUT4 rst_n_I_0_1_lut (.A(rst_n_in_c), .Z(rst_n_N_222)) /* synthesis lut_function=(!(A)) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(44[6:12])
    defparam rst_n_I_0_1_lut.init = 16'h5555;
    LUT4 i1477_4_lut (.A(n1571), .B(cnt[8]), .C(n12), .D(n8), .Z(clk_in_c_enable_5)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i1477_4_lut.init = 16'h4000;
    LUT4 i11_4_lut (.A(cnt[10]), .B(n22), .C(n18), .D(cnt[14]), .Z(n1571)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i11_4_lut.init = 16'hfffe;
    LUT4 i5_4_lut (.A(cnt[5]), .B(cnt[17]), .C(cnt[13]), .D(cnt[16]), 
         .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i5_4_lut.init = 16'h8000;
    LUT4 i1_2_lut (.A(cnt[18]), .B(cnt[15]), .Z(n8)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut.init = 16'h8888;
    LUT4 i10_4_lut (.A(cnt[12]), .B(n20), .C(n14), .D(cnt[4]), .Z(n22)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i10_4_lut.init = 16'hfffe;
    LUT4 i6_2_lut (.A(cnt[9]), .B(cnt[3]), .Z(n18)) /* synthesis lut_function=(A+(B)) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i6_2_lut.init = 16'heeee;
    LUT4 i8_4_lut (.A(cnt[1]), .B(cnt[0]), .C(cnt[2]), .D(cnt[6]), .Z(n20)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i8_4_lut.init = 16'hfffe;
    CCU2D cnt_178_add_4_19 (.A0(cnt[17]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[18]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1482), .S0(n81[17]), .S1(n81[18]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178_add_4_19.INIT0 = 16'hfaaa;
    defparam cnt_178_add_4_19.INIT1 = 16'hfaaa;
    defparam cnt_178_add_4_19.INJECT1_0 = "NO";
    defparam cnt_178_add_4_19.INJECT1_1 = "NO";
    CCU2D cnt_178_add_4_17 (.A0(cnt[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[16]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1481), .COUT(n1482), .S0(n81[15]), .S1(n81[16]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178_add_4_17.INIT0 = 16'hfaaa;
    defparam cnt_178_add_4_17.INIT1 = 16'hfaaa;
    defparam cnt_178_add_4_17.INJECT1_0 = "NO";
    defparam cnt_178_add_4_17.INJECT1_1 = "NO";
    LUT4 i2_2_lut (.A(cnt[7]), .B(cnt[11]), .Z(n14)) /* synthesis lut_function=(A+(B)) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i2_2_lut.init = 16'heeee;
    LUT4 key_rst_I_0_2_lut (.A(key_rst), .B(key_down_c), .Z(key_an)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(16[16:32])
    defparam key_rst_I_0_2_lut.init = 16'h6666;
    CCU2D cnt_178_add_4_15 (.A0(cnt[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1480), .COUT(n1481), .S0(n81[13]), .S1(n81[14]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178_add_4_15.INIT0 = 16'hfaaa;
    defparam cnt_178_add_4_15.INIT1 = 16'hfaaa;
    defparam cnt_178_add_4_15.INJECT1_0 = "NO";
    defparam cnt_178_add_4_15.INJECT1_1 = "NO";
    CCU2D cnt_178_add_4_13 (.A0(cnt[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1479), .COUT(n1480), .S0(n81[11]), .S1(n81[12]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178_add_4_13.INIT0 = 16'hfaaa;
    defparam cnt_178_add_4_13.INIT1 = 16'hfaaa;
    defparam cnt_178_add_4_13.INJECT1_0 = "NO";
    defparam cnt_178_add_4_13.INJECT1_1 = "NO";
    CCU2D cnt_178_add_4_11 (.A0(cnt[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1478), 
          .COUT(n1479), .S0(n81[9]), .S1(n81[10]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178_add_4_11.INIT0 = 16'hfaaa;
    defparam cnt_178_add_4_11.INIT1 = 16'hfaaa;
    defparam cnt_178_add_4_11.INJECT1_0 = "NO";
    defparam cnt_178_add_4_11.INJECT1_1 = "NO";
    FD1S3IX cnt_178__i18 (.D(n81[18]), .CK(clk_in_c), .CD(key_an), .Q(cnt[18])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i18.GSR = "ENABLED";
    CCU2D cnt_178_add_4_9 (.A0(cnt[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1477), 
          .COUT(n1478), .S0(n81[7]), .S1(n81[8]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178_add_4_9.INIT0 = 16'hfaaa;
    defparam cnt_178_add_4_9.INIT1 = 16'hfaaa;
    defparam cnt_178_add_4_9.INJECT1_0 = "NO";
    defparam cnt_178_add_4_9.INJECT1_1 = "NO";
    LUT4 i1_4_lut_rep_11 (.A(\duty[0] ), .B(n1898), .C(n6), .D(\duty[2] ), 
         .Z(n1894)) /* synthesis lut_function=(A (B)+!A (B (C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(40[19:40])
    defparam i1_4_lut_rep_11.init = 16'hccc8;
    FD1S3IX cnt_178__i17 (.D(n81[17]), .CK(clk_in_c), .CD(key_an), .Q(cnt[17])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i17.GSR = "ENABLED";
    FD1S3IX cnt_178__i16 (.D(n81[16]), .CK(clk_in_c), .CD(key_an), .Q(cnt[16])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i16.GSR = "ENABLED";
    FD1S3IX cnt_178__i15 (.D(n81[15]), .CK(clk_in_c), .CD(key_an), .Q(cnt[15])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i15.GSR = "ENABLED";
    FD1S3IX cnt_178__i14 (.D(n81[14]), .CK(clk_in_c), .CD(key_an), .Q(cnt[14])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i14.GSR = "ENABLED";
    FD1S3IX cnt_178__i13 (.D(n81[13]), .CK(clk_in_c), .CD(key_an), .Q(cnt[13])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i13.GSR = "ENABLED";
    FD1S3IX cnt_178__i12 (.D(n81[12]), .CK(clk_in_c), .CD(key_an), .Q(cnt[12])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i12.GSR = "ENABLED";
    FD1S3IX cnt_178__i11 (.D(n81[11]), .CK(clk_in_c), .CD(key_an), .Q(cnt[11])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i11.GSR = "ENABLED";
    FD1S3IX cnt_178__i10 (.D(n81[10]), .CK(clk_in_c), .CD(key_an), .Q(cnt[10])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i10.GSR = "ENABLED";
    FD1S3IX cnt_178__i9 (.D(n81[9]), .CK(clk_in_c), .CD(key_an), .Q(cnt[9])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i9.GSR = "ENABLED";
    FD1S3IX cnt_178__i8 (.D(n81[8]), .CK(clk_in_c), .CD(key_an), .Q(cnt[8])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i8.GSR = "ENABLED";
    FD1S3IX cnt_178__i7 (.D(n81[7]), .CK(clk_in_c), .CD(key_an), .Q(cnt[7])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i7.GSR = "ENABLED";
    FD1S3IX cnt_178__i6 (.D(n81[6]), .CK(clk_in_c), .CD(key_an), .Q(cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i6.GSR = "ENABLED";
    FD1S3IX cnt_178__i5 (.D(n81[5]), .CK(clk_in_c), .CD(key_an), .Q(cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i5.GSR = "ENABLED";
    FD1S3IX cnt_178__i4 (.D(n81[4]), .CK(clk_in_c), .CD(key_an), .Q(cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i4.GSR = "ENABLED";
    FD1S3IX cnt_178__i3 (.D(n81[3]), .CK(clk_in_c), .CD(key_an), .Q(cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i3.GSR = "ENABLED";
    FD1S3IX cnt_178__i2 (.D(n81[2]), .CK(clk_in_c), .CD(key_an), .Q(cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i2.GSR = "ENABLED";
    FD1S3IX cnt_178__i1 (.D(n81[1]), .CK(clk_in_c), .CD(key_an), .Q(cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178__i1.GSR = "ENABLED";
    CCU2D cnt_178_add_4_7 (.A0(cnt[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1476), 
          .COUT(n1477), .S0(n81[5]), .S1(n81[6]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178_add_4_7.INIT0 = 16'hfaaa;
    defparam cnt_178_add_4_7.INIT1 = 16'hfaaa;
    defparam cnt_178_add_4_7.INJECT1_0 = "NO";
    defparam cnt_178_add_4_7.INJECT1_1 = "NO";
    CCU2D cnt_178_add_4_5 (.A0(cnt[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1475), 
          .COUT(n1476), .S0(n81[3]), .S1(n81[4]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178_add_4_5.INIT0 = 16'hfaaa;
    defparam cnt_178_add_4_5.INIT1 = 16'hfaaa;
    defparam cnt_178_add_4_5.INJECT1_0 = "NO";
    defparam cnt_178_add_4_5.INJECT1_1 = "NO";
    CCU2D cnt_178_add_4_3 (.A0(cnt[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1474), 
          .COUT(n1475), .S0(n81[1]), .S1(n81[2]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_178_add_4_3.INIT0 = 16'hfaaa;
    defparam cnt_178_add_4_3.INIT1 = 16'hfaaa;
    defparam cnt_178_add_4_3.INJECT1_0 = "NO";
    defparam cnt_178_add_4_3.INJECT1_1 = "NO";
    
endmodule
//
// Verilog Description of module breath_led
//

module breath_led (cnt2, clk_in_c, GND_net, \breath_led_N_88[3] , \breath_led_N_88[4] , 
            \breath_led_N_88[0] , \breath_led_N_88[2] , \breath_led_N_88[1] , 
            \breath_led_N_88[11] , \breath_led_N_88[12] , \breath_led_N_88[9] , 
            \breath_led_N_88[10] , \breath_led_N_88[7] , \breath_led_N_88[8] , 
            \breath_led_N_88[5] , \breath_led_N_88[6] ) /* synthesis syn_module_defined=1 */ ;
    output [12:0]cnt2;
    input clk_in_c;
    input GND_net;
    output \breath_led_N_88[3] ;
    output \breath_led_N_88[4] ;
    output \breath_led_N_88[0] ;
    output \breath_led_N_88[2] ;
    output \breath_led_N_88[1] ;
    output \breath_led_N_88[11] ;
    output \breath_led_N_88[12] ;
    output \breath_led_N_88[9] ;
    output \breath_led_N_88[10] ;
    output \breath_led_N_88[7] ;
    output \breath_led_N_88[8] ;
    output \breath_led_N_88[5] ;
    output \breath_led_N_88[6] ;
    
    wire clk_in_c /* synthesis SET_AS_NETWORK=clk_in_c, is_clock=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(3[11:17])
    wire [12:0]cnt1;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(28[12:16])
    
    wire n1739, clk_in_c_enable_20;
    wire [12:0]n330;
    
    wire n1712, n1721, n1724, cnt1_12__N_72, n20, n4, n1459, n1460, 
        dir_cnt2, n580, n1890;
    wire [11:0]n53;
    
    wire n1710, n211, n8, n1515, n1747, n1895, n1458, dir_cnt2_N_125, 
        n1514, n1513, n1512, n1452, n1453, n1457, n1511, n1510, 
        n1456, n1573, n780, n1455, n1454, n15, n14, n782, n1463, 
        n1462, n1461, n4_adj_269;
    
    LUT4 i1434_2_lut (.A(cnt1[11]), .B(cnt1[7]), .Z(n1739)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1434_2_lut.init = 16'h8888;
    FD1P3AX cnt2_i0_i0 (.D(n330[0]), .SP(clk_in_c_enable_20), .CK(clk_in_c), 
            .Q(cnt2[0])) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=12, LSE_RCOL=2, LSE_LLINE=22, LSE_RLINE=27 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(46[11] 56[5])
    defparam cnt2_i0_i0.GSR = "ENABLED";
    LUT4 i1_4_lut (.A(n1712), .B(n1721), .C(cnt1[9]), .D(n1724), .Z(cnt1_12__N_72)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C))) */ ;
    defparam i1_4_lut.init = 16'hc8c0;
    LUT4 i1_2_lut (.A(n20), .B(cnt2[11]), .Z(n4)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut.init = 16'h8888;
    CCU2D add_179_3 (.A0(cnt1[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt1[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1459), 
          .COUT(n1460), .S0(\breath_led_N_88[3] ), .S1(\breath_led_N_88[4] ));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(60[22:38])
    defparam add_179_3.INIT0 = 16'h5aaa;
    defparam add_179_3.INIT1 = 16'h5555;
    defparam add_179_3.INJECT1_0 = "NO";
    defparam add_179_3.INJECT1_1 = "NO";
    FD1S3AX dir_cnt2_33 (.D(n580), .CK(clk_in_c), .Q(dir_cnt2));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(46[11] 56[5])
    defparam dir_cnt2_33.GSR = "ENABLED";
    LUT4 i2_3_lut_rep_7 (.A(cnt2[11]), .B(cnt2[10]), .C(n20), .Z(n1890)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i2_3_lut_rep_7.init = 16'h8080;
    FD1S3IX cnt1_172_173__i1 (.D(n53[0]), .CK(clk_in_c), .CD(cnt1_12__N_72), 
            .Q(\breath_led_N_88[0] )) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173__i1.GSR = "ENABLED";
    CCU2D add_179_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt1[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n1459), 
          .S1(\breath_led_N_88[2] ));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(60[22:38])
    defparam add_179_1.INIT0 = 16'hF000;
    defparam add_179_1.INIT1 = 16'h5555;
    defparam add_179_1.INJECT1_0 = "NO";
    defparam add_179_1.INJECT1_1 = "NO";
    LUT4 i3_3_lut_4_lut (.A(cnt1[9]), .B(n1710), .C(n211), .D(n1724), 
         .Z(n8)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(47[6:21])
    defparam i3_3_lut_4_lut.init = 16'h1000;
    CCU2D cnt1_172_173_add_4_13 (.A0(cnt1[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1515), .S0(n53[11]));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173_add_4_13.INIT0 = 16'hfaaa;
    defparam cnt1_172_173_add_4_13.INIT1 = 16'h0000;
    defparam cnt1_172_173_add_4_13.INJECT1_0 = "NO";
    defparam cnt1_172_173_add_4_13.INJECT1_1 = "NO";
    LUT4 i1442_4_lut (.A(cnt1[10]), .B(cnt1[8]), .C(cnt1[2]), .D(\breath_led_N_88[0] ), 
         .Z(n1747)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i1442_4_lut.init = 16'h8000;
    LUT4 i2_3_lut_rep_12 (.A(cnt1[2]), .B(\breath_led_N_88[0] ), .C(\breath_led_N_88[1] ), 
         .Z(n1895)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i2_3_lut_rep_12.init = 16'h8080;
    LUT4 i3_4_lut (.A(cnt1[6]), .B(cnt1[3]), .C(cnt1[4]), .D(cnt1[5]), 
         .Z(n1710)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(47[6:21])
    defparam i3_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut_4_lut (.A(cnt1[2]), .B(\breath_led_N_88[0] ), .C(\breath_led_N_88[1] ), 
         .D(n1710), .Z(n1712)) /* synthesis lut_function=(A (B (C+(D))+!B (D))+!A (D)) */ ;
    defparam i1_2_lut_4_lut.init = 16'hff80;
    LUT4 i1_2_lut_adj_14 (.A(cnt1[11]), .B(cnt1[10]), .Z(n1721)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_adj_14.init = 16'h8888;
    CCU2D add_131_15 (.A0(dir_cnt2), .B0(dir_cnt2_N_125), .C0(cnt2[12]), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1458), .S0(n330[12]));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(51[13] 54[7])
    defparam add_131_15.INIT0 = 16'h1e1e;
    defparam add_131_15.INIT1 = 16'h0000;
    defparam add_131_15.INJECT1_0 = "NO";
    defparam add_131_15.INJECT1_1 = "NO";
    CCU2D cnt1_172_173_add_4_11 (.A0(cnt1[9]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt1[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1514), .COUT(n1515), .S0(n53[9]), .S1(n53[10]));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173_add_4_11.INIT0 = 16'hfaaa;
    defparam cnt1_172_173_add_4_11.INIT1 = 16'hfaaa;
    defparam cnt1_172_173_add_4_11.INJECT1_0 = "NO";
    defparam cnt1_172_173_add_4_11.INJECT1_1 = "NO";
    CCU2D cnt1_172_173_add_4_9 (.A0(cnt1[7]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt1[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1513), .COUT(n1514), .S0(n53[7]), .S1(n53[8]));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173_add_4_9.INIT0 = 16'hfaaa;
    defparam cnt1_172_173_add_4_9.INIT1 = 16'hfaaa;
    defparam cnt1_172_173_add_4_9.INJECT1_0 = "NO";
    defparam cnt1_172_173_add_4_9.INJECT1_1 = "NO";
    LUT4 i574_4_lut (.A(dir_cnt2), .B(n1895), .C(n8), .D(n1721), .Z(n580)) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(46[11] 56[5])
    defparam i574_4_lut.init = 16'h6aaa;
    CCU2D cnt1_172_173_add_4_7 (.A0(cnt1[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt1[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1512), .COUT(n1513), .S0(n53[5]), .S1(n53[6]));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173_add_4_7.INIT0 = 16'hfaaa;
    defparam cnt1_172_173_add_4_7.INIT1 = 16'hfaaa;
    defparam cnt1_172_173_add_4_7.INJECT1_0 = "NO";
    defparam cnt1_172_173_add_4_7.INJECT1_1 = "NO";
    LUT4 i1_2_lut_adj_15 (.A(cnt1[8]), .B(cnt1[7]), .Z(n1724)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_adj_15.init = 16'h8888;
    CCU2D add_131_3 (.A0(dir_cnt2), .B0(dir_cnt2_N_125), .C0(cnt2[0]), 
          .D0(GND_net), .A1(cnt2[1]), .B1(cnt2[12]), .C1(n1890), .D1(dir_cnt2), 
          .CIN(n1452), .COUT(n1453), .S0(n330[0]), .S1(n330[1]));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(51[13] 54[7])
    defparam add_131_3.INIT0 = 16'he1e1;
    defparam add_131_3.INIT1 = 16'h5556;
    defparam add_131_3.INJECT1_0 = "NO";
    defparam add_131_3.INJECT1_1 = "NO";
    CCU2D add_131_13 (.A0(cnt2[10]), .B0(cnt2[12]), .C0(n1890), .D0(dir_cnt2), 
          .A1(cnt2[11]), .B1(cnt2[12]), .C1(n1890), .D1(dir_cnt2), .CIN(n1457), 
          .COUT(n1458), .S0(n330[10]), .S1(n330[11]));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(51[13] 54[7])
    defparam add_131_13.INIT0 = 16'h5556;
    defparam add_131_13.INIT1 = 16'h5556;
    defparam add_131_13.INJECT1_0 = "NO";
    defparam add_131_13.INJECT1_1 = "NO";
    CCU2D cnt1_172_173_add_4_5 (.A0(cnt1[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt1[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1511), .COUT(n1512), .S0(n53[3]), .S1(n53[4]));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173_add_4_5.INIT0 = 16'hfaaa;
    defparam cnt1_172_173_add_4_5.INIT1 = 16'hfaaa;
    defparam cnt1_172_173_add_4_5.INJECT1_0 = "NO";
    defparam cnt1_172_173_add_4_5.INJECT1_1 = "NO";
    CCU2D add_131_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(n4), .B1(cnt2[10]), .C1(cnt2[12]), .D1(dir_cnt2), .COUT(n1452));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(51[13] 54[7])
    defparam add_131_1.INIT0 = 16'hF000;
    defparam add_131_1.INIT1 = 16'h0007;
    defparam add_131_1.INJECT1_0 = "NO";
    defparam add_131_1.INJECT1_1 = "NO";
    CCU2D cnt1_172_173_add_4_3 (.A0(\breath_led_N_88[1] ), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(cnt1[2]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n1510), .COUT(n1511), .S0(n53[1]), .S1(n53[2]));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173_add_4_3.INIT0 = 16'hfaaa;
    defparam cnt1_172_173_add_4_3.INIT1 = 16'hfaaa;
    defparam cnt1_172_173_add_4_3.INJECT1_0 = "NO";
    defparam cnt1_172_173_add_4_3.INJECT1_1 = "NO";
    CCU2D add_131_11 (.A0(cnt2[8]), .B0(cnt2[12]), .C0(n1890), .D0(dir_cnt2), 
          .A1(cnt2[9]), .B1(cnt2[12]), .C1(n1890), .D1(dir_cnt2), .CIN(n1456), 
          .COUT(n1457), .S0(n330[8]), .S1(n330[9]));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(51[13] 54[7])
    defparam add_131_11.INIT0 = 16'h5556;
    defparam add_131_11.INIT1 = 16'h5556;
    defparam add_131_11.INJECT1_0 = "NO";
    defparam add_131_11.INJECT1_1 = "NO";
    CCU2D cnt1_172_173_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(\breath_led_N_88[0] ), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n1510), .S1(n53[0]));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173_add_4_1.INIT0 = 16'hF000;
    defparam cnt1_172_173_add_4_1.INIT1 = 16'h0555;
    defparam cnt1_172_173_add_4_1.INJECT1_0 = "NO";
    defparam cnt1_172_173_add_4_1.INJECT1_1 = "NO";
    FD1S3IX cnt1_172_173__i12 (.D(n53[11]), .CK(clk_in_c), .CD(cnt1_12__N_72), 
            .Q(cnt1[11])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173__i12.GSR = "ENABLED";
    LUT4 i159_4_lut (.A(dir_cnt2_N_125), .B(n1573), .C(dir_cnt2), .D(n780), 
         .Z(n211)) /* synthesis lut_function=(!(A (B (C)+!B (C (D)))+!A (B+((D)+!C)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(51[13] 54[7])
    defparam i159_4_lut.init = 16'h0a3a;
    CCU2D add_131_9 (.A0(cnt2[6]), .B0(cnt2[12]), .C0(n1890), .D0(dir_cnt2), 
          .A1(cnt2[7]), .B1(cnt2[12]), .C1(n1890), .D1(dir_cnt2), .CIN(n1455), 
          .COUT(n1456), .S0(n330[6]), .S1(n330[7]));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(51[13] 54[7])
    defparam add_131_9.INIT0 = 16'h5556;
    defparam add_131_9.INIT1 = 16'h5556;
    defparam add_131_9.INJECT1_0 = "NO";
    defparam add_131_9.INJECT1_1 = "NO";
    FD1S3IX cnt1_172_173__i11 (.D(n53[10]), .CK(clk_in_c), .CD(cnt1_12__N_72), 
            .Q(cnt1[10])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173__i11.GSR = "ENABLED";
    FD1S3IX cnt1_172_173__i10 (.D(n53[9]), .CK(clk_in_c), .CD(cnt1_12__N_72), 
            .Q(cnt1[9])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173__i10.GSR = "ENABLED";
    FD1S3IX cnt1_172_173__i9 (.D(n53[8]), .CK(clk_in_c), .CD(cnt1_12__N_72), 
            .Q(cnt1[8])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173__i9.GSR = "ENABLED";
    FD1S3IX cnt1_172_173__i8 (.D(n53[7]), .CK(clk_in_c), .CD(cnt1_12__N_72), 
            .Q(cnt1[7])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173__i8.GSR = "ENABLED";
    FD1S3IX cnt1_172_173__i7 (.D(n53[6]), .CK(clk_in_c), .CD(cnt1_12__N_72), 
            .Q(cnt1[6])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173__i7.GSR = "ENABLED";
    FD1S3IX cnt1_172_173__i6 (.D(n53[5]), .CK(clk_in_c), .CD(cnt1_12__N_72), 
            .Q(cnt1[5])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173__i6.GSR = "ENABLED";
    FD1S3IX cnt1_172_173__i5 (.D(n53[4]), .CK(clk_in_c), .CD(cnt1_12__N_72), 
            .Q(cnt1[4])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173__i5.GSR = "ENABLED";
    FD1S3IX cnt1_172_173__i4 (.D(n53[3]), .CK(clk_in_c), .CD(cnt1_12__N_72), 
            .Q(cnt1[3])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173__i4.GSR = "ENABLED";
    FD1S3IX cnt1_172_173__i3 (.D(n53[2]), .CK(clk_in_c), .CD(cnt1_12__N_72), 
            .Q(cnt1[2])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173__i3.GSR = "ENABLED";
    FD1S3IX cnt1_172_173__i2 (.D(n53[1]), .CK(clk_in_c), .CD(cnt1_12__N_72), 
            .Q(\breath_led_N_88[1] )) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(35[14:23])
    defparam cnt1_172_173__i2.GSR = "ENABLED";
    CCU2D add_131_7 (.A0(cnt2[4]), .B0(cnt2[12]), .C0(n1890), .D0(dir_cnt2), 
          .A1(cnt2[5]), .B1(cnt2[12]), .C1(n1890), .D1(dir_cnt2), .CIN(n1454), 
          .COUT(n1455), .S0(n330[4]), .S1(n330[5]));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(51[13] 54[7])
    defparam add_131_7.INIT0 = 16'h5556;
    defparam add_131_7.INIT1 = 16'h5556;
    defparam add_131_7.INJECT1_0 = "NO";
    defparam add_131_7.INJECT1_1 = "NO";
    LUT4 i8_4_lut (.A(n15), .B(cnt2[12]), .C(n14), .D(cnt2[1]), .Z(n1573)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(52[8:15])
    defparam i8_4_lut.init = 16'hfffe;
    LUT4 i6_4_lut (.A(cnt2[10]), .B(cnt2[7]), .C(cnt2[2]), .D(cnt2[8]), 
         .Z(n15)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(52[8:15])
    defparam i6_4_lut.init = 16'hfffe;
    LUT4 i5_3_lut (.A(cnt2[11]), .B(cnt2[0]), .C(cnt2[9]), .Z(n14)) /* synthesis lut_function=(A+(B+(C))) */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(52[8:15])
    defparam i5_3_lut.init = 16'hfefe;
    LUT4 i3_4_lut_adj_16 (.A(cnt2[5]), .B(cnt2[3]), .C(cnt2[6]), .D(cnt2[4]), 
         .Z(n780)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i3_4_lut_adj_16.init = 16'hfffe;
    LUT4 i299_4_lut (.A(cnt2[8]), .B(cnt2[9]), .C(cnt2[7]), .D(n782), 
         .Z(n20)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;
    defparam i299_4_lut.init = 16'heccc;
    CCU2D add_131_5 (.A0(cnt2[2]), .B0(cnt2[12]), .C0(n1890), .D0(dir_cnt2), 
          .A1(cnt2[3]), .B1(cnt2[12]), .C1(n1890), .D1(dir_cnt2), .CIN(n1453), 
          .COUT(n1454), .S0(n330[2]), .S1(n330[3]));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(51[13] 54[7])
    defparam add_131_5.INIT0 = 16'h5556;
    defparam add_131_5.INIT1 = 16'h5556;
    defparam add_131_5.INJECT1_0 = "NO";
    defparam add_131_5.INJECT1_1 = "NO";
    LUT4 i1_4_lut_adj_17 (.A(cnt2[2]), .B(n780), .C(cnt2[1]), .D(cnt2[0]), 
         .Z(n782)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;
    defparam i1_4_lut_adj_17.init = 16'heccc;
    CCU2D add_179_11 (.A0(cnt1[11]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1463), 
          .S0(\breath_led_N_88[11] ), .S1(\breath_led_N_88[12] ));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(60[22:38])
    defparam add_179_11.INIT0 = 16'h5aaa;
    defparam add_179_11.INIT1 = 16'h0000;
    defparam add_179_11.INJECT1_0 = "NO";
    defparam add_179_11.INJECT1_1 = "NO";
    CCU2D add_179_9 (.A0(cnt1[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt1[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1462), 
          .COUT(n1463), .S0(\breath_led_N_88[9] ), .S1(\breath_led_N_88[10] ));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(60[22:38])
    defparam add_179_9.INIT0 = 16'h5555;
    defparam add_179_9.INIT1 = 16'h5aaa;
    defparam add_179_9.INJECT1_0 = "NO";
    defparam add_179_9.INJECT1_1 = "NO";
    CCU2D add_179_7 (.A0(cnt1[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt1[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1461), 
          .COUT(n1462), .S0(\breath_led_N_88[7] ), .S1(\breath_led_N_88[8] ));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(60[22:38])
    defparam add_179_7.INIT0 = 16'h5555;
    defparam add_179_7.INIT1 = 16'h5aaa;
    defparam add_179_7.INJECT1_0 = "NO";
    defparam add_179_7.INJECT1_1 = "NO";
    CCU2D add_179_5 (.A0(cnt1[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt1[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1460), 
          .COUT(n1461), .S0(\breath_led_N_88[5] ), .S1(\breath_led_N_88[6] ));   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(60[22:38])
    defparam add_179_5.INIT0 = 16'h5555;
    defparam add_179_5.INIT1 = 16'h5aaa;
    defparam add_179_5.INJECT1_0 = "NO";
    defparam add_179_5.INJECT1_1 = "NO";
    FD1P3AX cnt2_i0_i12 (.D(n330[12]), .SP(clk_in_c_enable_20), .CK(clk_in_c), 
            .Q(cnt2[12])) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=12, LSE_RCOL=2, LSE_LLINE=22, LSE_RLINE=27 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(46[11] 56[5])
    defparam cnt2_i0_i12.GSR = "ENABLED";
    FD1P3AX cnt2_i0_i11 (.D(n330[11]), .SP(clk_in_c_enable_20), .CK(clk_in_c), 
            .Q(cnt2[11])) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=12, LSE_RCOL=2, LSE_LLINE=22, LSE_RLINE=27 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(46[11] 56[5])
    defparam cnt2_i0_i11.GSR = "ENABLED";
    FD1P3AX cnt2_i0_i10 (.D(n330[10]), .SP(clk_in_c_enable_20), .CK(clk_in_c), 
            .Q(cnt2[10])) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=12, LSE_RCOL=2, LSE_LLINE=22, LSE_RLINE=27 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(46[11] 56[5])
    defparam cnt2_i0_i10.GSR = "ENABLED";
    FD1P3AX cnt2_i0_i9 (.D(n330[9]), .SP(clk_in_c_enable_20), .CK(clk_in_c), 
            .Q(cnt2[9])) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=12, LSE_RCOL=2, LSE_LLINE=22, LSE_RLINE=27 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(46[11] 56[5])
    defparam cnt2_i0_i9.GSR = "ENABLED";
    FD1P3AX cnt2_i0_i8 (.D(n330[8]), .SP(clk_in_c_enable_20), .CK(clk_in_c), 
            .Q(cnt2[8])) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=12, LSE_RCOL=2, LSE_LLINE=22, LSE_RLINE=27 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(46[11] 56[5])
    defparam cnt2_i0_i8.GSR = "ENABLED";
    FD1P3AX cnt2_i0_i7 (.D(n330[7]), .SP(clk_in_c_enable_20), .CK(clk_in_c), 
            .Q(cnt2[7])) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=12, LSE_RCOL=2, LSE_LLINE=22, LSE_RLINE=27 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(46[11] 56[5])
    defparam cnt2_i0_i7.GSR = "ENABLED";
    FD1P3AX cnt2_i0_i6 (.D(n330[6]), .SP(clk_in_c_enable_20), .CK(clk_in_c), 
            .Q(cnt2[6])) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=12, LSE_RCOL=2, LSE_LLINE=22, LSE_RLINE=27 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(46[11] 56[5])
    defparam cnt2_i0_i6.GSR = "ENABLED";
    FD1P3AX cnt2_i0_i5 (.D(n330[5]), .SP(clk_in_c_enable_20), .CK(clk_in_c), 
            .Q(cnt2[5])) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=12, LSE_RCOL=2, LSE_LLINE=22, LSE_RLINE=27 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(46[11] 56[5])
    defparam cnt2_i0_i5.GSR = "ENABLED";
    FD1P3AX cnt2_i0_i4 (.D(n330[4]), .SP(clk_in_c_enable_20), .CK(clk_in_c), 
            .Q(cnt2[4])) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=12, LSE_RCOL=2, LSE_LLINE=22, LSE_RLINE=27 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(46[11] 56[5])
    defparam cnt2_i0_i4.GSR = "ENABLED";
    FD1P3AX cnt2_i0_i3 (.D(n330[3]), .SP(clk_in_c_enable_20), .CK(clk_in_c), 
            .Q(cnt2[3])) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=12, LSE_RCOL=2, LSE_LLINE=22, LSE_RLINE=27 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(46[11] 56[5])
    defparam cnt2_i0_i3.GSR = "ENABLED";
    FD1P3AX cnt2_i0_i2 (.D(n330[2]), .SP(clk_in_c_enable_20), .CK(clk_in_c), 
            .Q(cnt2[2])) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=12, LSE_RCOL=2, LSE_LLINE=22, LSE_RLINE=27 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(46[11] 56[5])
    defparam cnt2_i0_i2.GSR = "ENABLED";
    FD1P3AX cnt2_i0_i1 (.D(n330[1]), .SP(clk_in_c_enable_20), .CK(clk_in_c), 
            .Q(cnt2[1])) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=12, LSE_RCOL=2, LSE_LLINE=22, LSE_RLINE=27 */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(46[11] 56[5])
    defparam cnt2_i0_i1.GSR = "ENABLED";
    LUT4 i1472_4_lut (.A(\breath_led_N_88[1] ), .B(n4_adj_269), .C(n1747), 
         .D(n1739), .Z(clk_in_c_enable_20)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;
    defparam i1472_4_lut.init = 16'h2000;
    LUT4 i1_2_lut_3_lut (.A(cnt1[9]), .B(n1710), .C(n211), .Z(n4_adj_269)) /* synthesis lut_function=(A+(B+(C))) */ ;   // d:/git/oschina/step_mxo2/labs/src/breath_led.v(47[6:21])
    defparam i1_2_lut_3_lut.init = 16'hfefe;
    LUT4 i296_2_lut_4_lut (.A(cnt2[11]), .B(cnt2[10]), .C(n20), .D(cnt2[12]), 
         .Z(dir_cnt2_N_125)) /* synthesis lut_function=(A (B (C+(D))+!B (D))+!A (D)) */ ;
    defparam i296_2_lut_4_lut.init = 16'hff80;
    
endmodule
//
// Verilog Description of module divide
//

module divide (GND_net, clk_in_c, rst_n_N_222, \div_clko[0] , clk_N_161, 
            rst_n_in_c) /* synthesis syn_module_defined=1 */ ;
    input GND_net;
    input clk_in_c;
    input rst_n_N_222;
    output \div_clko[0] ;
    input clk_N_161;
    input rst_n_in_c;
    
    wire clk_in_c /* synthesis SET_AS_NETWORK=clk_in_c, is_clock=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(3[11:17])
    wire \div_clko[0]  /* synthesis SET_AS_NETWORK=div_clko[0], is_clock=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(19[12:20])
    wire clk_N_161 /* synthesis is_inv_clock=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(55[26:31])
    
    wire n1501;
    wire [15:0]cnt_p;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(55[20:25])
    wire [15:0]n69;
    
    wire n1500, n1499, n1498;
    wire [15:0]cnt_n;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(55[26:31])
    
    wire n4, n1497, n1496, n1495, n1494, clk_p, clk_p_N_197, clk_n, 
        clk_n_N_200, n218, n221;
    wire [15:0]n69_adj_268;
    
    wire n1709, n4_adj_250, n1707, n15, n14, n15_adj_251, n14_adj_252, 
        n1509, n1508, n1507, n1704, n1506, n1505, n10, n1753, 
        n1504, n1706, n1503, n1502, n7, n1524, n8;
    
    CCU2D cnt_p_175_add_4_17 (.A0(cnt_p[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1501), .S0(n69[15]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175_add_4_17.INIT0 = 16'hfaaa;
    defparam cnt_p_175_add_4_17.INIT1 = 16'h0000;
    defparam cnt_p_175_add_4_17.INJECT1_0 = "NO";
    defparam cnt_p_175_add_4_17.INJECT1_1 = "NO";
    CCU2D cnt_p_175_add_4_15 (.A0(cnt_p[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[14]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n1500), .COUT(n1501), .S0(n69[13]), .S1(n69[14]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175_add_4_15.INIT0 = 16'hfaaa;
    defparam cnt_p_175_add_4_15.INIT1 = 16'hfaaa;
    defparam cnt_p_175_add_4_15.INJECT1_0 = "NO";
    defparam cnt_p_175_add_4_15.INJECT1_1 = "NO";
    CCU2D cnt_p_175_add_4_13 (.A0(cnt_p[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[12]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n1499), .COUT(n1500), .S0(n69[11]), .S1(n69[12]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175_add_4_13.INIT0 = 16'hfaaa;
    defparam cnt_p_175_add_4_13.INIT1 = 16'hfaaa;
    defparam cnt_p_175_add_4_13.INJECT1_0 = "NO";
    defparam cnt_p_175_add_4_13.INJECT1_1 = "NO";
    CCU2D cnt_p_175_add_4_11 (.A0(cnt_p[9]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[10]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n1498), .COUT(n1499), .S0(n69[9]), .S1(n69[10]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175_add_4_11.INIT0 = 16'hfaaa;
    defparam cnt_p_175_add_4_11.INIT1 = 16'hfaaa;
    defparam cnt_p_175_add_4_11.INJECT1_0 = "NO";
    defparam cnt_p_175_add_4_11.INJECT1_1 = "NO";
    LUT4 i1_4_lut (.A(cnt_n[0]), .B(cnt_n[3]), .C(cnt_n[2]), .D(cnt_n[1]), 
         .Z(n4)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i1_4_lut.init = 16'hfcec;
    CCU2D cnt_p_175_add_4_9 (.A0(cnt_p[7]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1497), .COUT(n1498), .S0(n69[7]), .S1(n69[8]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175_add_4_9.INIT0 = 16'hfaaa;
    defparam cnt_p_175_add_4_9.INIT1 = 16'hfaaa;
    defparam cnt_p_175_add_4_9.INJECT1_0 = "NO";
    defparam cnt_p_175_add_4_9.INJECT1_1 = "NO";
    CCU2D cnt_p_175_add_4_7 (.A0(cnt_p[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1496), .COUT(n1497), .S0(n69[5]), .S1(n69[6]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175_add_4_7.INIT0 = 16'hfaaa;
    defparam cnt_p_175_add_4_7.INIT1 = 16'hfaaa;
    defparam cnt_p_175_add_4_7.INJECT1_0 = "NO";
    defparam cnt_p_175_add_4_7.INJECT1_1 = "NO";
    CCU2D cnt_p_175_add_4_5 (.A0(cnt_p[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1495), .COUT(n1496), .S0(n69[3]), .S1(n69[4]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175_add_4_5.INIT0 = 16'hfaaa;
    defparam cnt_p_175_add_4_5.INIT1 = 16'hfaaa;
    defparam cnt_p_175_add_4_5.INJECT1_0 = "NO";
    defparam cnt_p_175_add_4_5.INJECT1_1 = "NO";
    CCU2D cnt_p_175_add_4_3 (.A0(cnt_p[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1494), .COUT(n1495), .S0(n69[1]), .S1(n69[2]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175_add_4_3.INIT0 = 16'hfaaa;
    defparam cnt_p_175_add_4_3.INIT1 = 16'hfaaa;
    defparam cnt_p_175_add_4_3.INJECT1_0 = "NO";
    defparam cnt_p_175_add_4_3.INJECT1_1 = "NO";
    FD1S3IX clk_p_31 (.D(clk_p_N_197), .CK(clk_in_c), .CD(rst_n_N_222), 
            .Q(clk_p));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(79[9] 87[6])
    defparam clk_p_31.GSR = "DISABLED";
    LUT4 clk_p_I_0_2_lut (.A(clk_p), .B(clk_n), .Z(\div_clko[0] )) /* synthesis lut_function=(A (B)) */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(58[36:49])
    defparam clk_p_I_0_2_lut.init = 16'h8888;
    CCU2D cnt_p_175_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_p[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .COUT(n1494), .S1(n69[0]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175_add_4_1.INIT0 = 16'hF000;
    defparam cnt_p_175_add_4_1.INIT1 = 16'h0555;
    defparam cnt_p_175_add_4_1.INJECT1_0 = "NO";
    defparam cnt_p_175_add_4_1.INJECT1_1 = "NO";
    FD1S3IX clk_n_32 (.D(clk_n_N_200), .CK(clk_N_161), .CD(rst_n_N_222), 
            .Q(clk_n));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(89[9] 97[6])
    defparam clk_n_32.GSR = "DISABLED";
    FD1S3IX cnt_p_175__i0 (.D(n69[0]), .CK(clk_in_c), .CD(n218), .Q(cnt_p[0])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175__i0.GSR = "DISABLED";
    FD1S3IX cnt_n_174__i0 (.D(n69_adj_268[0]), .CK(clk_N_161), .CD(n221), 
            .Q(cnt_n[0])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174__i0.GSR = "DISABLED";
    LUT4 i1_4_lut_adj_7 (.A(cnt_p[4]), .B(n1709), .C(cnt_p[5]), .D(n4_adj_250), 
         .Z(clk_p_N_197)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(65[13:25])
    defparam i1_4_lut_adj_7.init = 16'hfcec;
    LUT4 i1_2_lut (.A(cnt_p[6]), .B(n1707), .Z(n1709)) /* synthesis lut_function=(A+(B)) */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(65[13:25])
    defparam i1_2_lut.init = 16'heeee;
    LUT4 i6_4_lut (.A(cnt_n[14]), .B(cnt_n[15]), .C(cnt_n[9]), .D(cnt_n[7]), 
         .Z(n15)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(74[13:25])
    defparam i6_4_lut.init = 16'hfffe;
    LUT4 i5_3_lut (.A(cnt_n[12]), .B(cnt_n[10]), .C(cnt_n[11]), .Z(n14)) /* synthesis lut_function=(A+(B+(C))) */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(74[13:25])
    defparam i5_3_lut.init = 16'hfefe;
    LUT4 i1_4_lut_adj_8 (.A(cnt_p[0]), .B(cnt_p[3]), .C(cnt_p[2]), .D(cnt_p[1]), 
         .Z(n4_adj_250)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i1_4_lut_adj_8.init = 16'hfcec;
    LUT4 i8_4_lut (.A(n15_adj_251), .B(cnt_p[13]), .C(n14_adj_252), .D(cnt_p[8]), 
         .Z(n1707)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(65[13:25])
    defparam i8_4_lut.init = 16'hfffe;
    LUT4 i6_4_lut_adj_9 (.A(cnt_p[14]), .B(cnt_p[15]), .C(cnt_p[9]), .D(cnt_p[7]), 
         .Z(n15_adj_251)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(65[13:25])
    defparam i6_4_lut_adj_9.init = 16'hfffe;
    FD1S3IX cnt_n_174__i15 (.D(n69_adj_268[15]), .CK(clk_N_161), .CD(n221), 
            .Q(cnt_n[15])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174__i15.GSR = "DISABLED";
    CCU2D cnt_n_174_add_4_17 (.A0(cnt_n[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1509), .S0(n69_adj_268[15]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174_add_4_17.INIT0 = 16'hfaaa;
    defparam cnt_n_174_add_4_17.INIT1 = 16'h0000;
    defparam cnt_n_174_add_4_17.INJECT1_0 = "NO";
    defparam cnt_n_174_add_4_17.INJECT1_1 = "NO";
    CCU2D cnt_n_174_add_4_15 (.A0(cnt_n[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[14]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n1508), .COUT(n1509), .S0(n69_adj_268[13]), 
          .S1(n69_adj_268[14]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174_add_4_15.INIT0 = 16'hfaaa;
    defparam cnt_n_174_add_4_15.INIT1 = 16'hfaaa;
    defparam cnt_n_174_add_4_15.INJECT1_0 = "NO";
    defparam cnt_n_174_add_4_15.INJECT1_1 = "NO";
    CCU2D cnt_n_174_add_4_13 (.A0(cnt_n[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[12]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n1507), .COUT(n1508), .S0(n69_adj_268[11]), 
          .S1(n69_adj_268[12]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174_add_4_13.INIT0 = 16'hfaaa;
    defparam cnt_n_174_add_4_13.INIT1 = 16'hfaaa;
    defparam cnt_n_174_add_4_13.INJECT1_0 = "NO";
    defparam cnt_n_174_add_4_13.INJECT1_1 = "NO";
    FD1S3IX cnt_n_174__i14 (.D(n69_adj_268[14]), .CK(clk_N_161), .CD(n221), 
            .Q(cnt_n[14])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174__i14.GSR = "DISABLED";
    FD1S3IX cnt_n_174__i13 (.D(n69_adj_268[13]), .CK(clk_N_161), .CD(n221), 
            .Q(cnt_n[13])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174__i13.GSR = "DISABLED";
    FD1S3IX cnt_n_174__i12 (.D(n69_adj_268[12]), .CK(clk_N_161), .CD(n221), 
            .Q(cnt_n[12])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174__i12.GSR = "DISABLED";
    FD1S3IX cnt_n_174__i11 (.D(n69_adj_268[11]), .CK(clk_N_161), .CD(n221), 
            .Q(cnt_n[11])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174__i11.GSR = "DISABLED";
    FD1S3IX cnt_n_174__i10 (.D(n69_adj_268[10]), .CK(clk_N_161), .CD(n221), 
            .Q(cnt_n[10])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174__i10.GSR = "DISABLED";
    FD1S3IX cnt_n_174__i9 (.D(n69_adj_268[9]), .CK(clk_N_161), .CD(n221), 
            .Q(cnt_n[9])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174__i9.GSR = "DISABLED";
    FD1S3IX cnt_n_174__i8 (.D(n69_adj_268[8]), .CK(clk_N_161), .CD(n221), 
            .Q(cnt_n[8])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174__i8.GSR = "DISABLED";
    FD1S3IX cnt_n_174__i7 (.D(n69_adj_268[7]), .CK(clk_N_161), .CD(n221), 
            .Q(cnt_n[7])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174__i7.GSR = "DISABLED";
    FD1S3IX cnt_n_174__i6 (.D(n69_adj_268[6]), .CK(clk_N_161), .CD(n221), 
            .Q(cnt_n[6])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174__i6.GSR = "DISABLED";
    FD1S3IX cnt_n_174__i5 (.D(n69_adj_268[5]), .CK(clk_N_161), .CD(n221), 
            .Q(cnt_n[5])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174__i5.GSR = "DISABLED";
    FD1S3IX cnt_n_174__i4 (.D(n69_adj_268[4]), .CK(clk_N_161), .CD(n221), 
            .Q(cnt_n[4])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174__i4.GSR = "DISABLED";
    FD1S3IX cnt_n_174__i3 (.D(n69_adj_268[3]), .CK(clk_N_161), .CD(n221), 
            .Q(cnt_n[3])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174__i3.GSR = "DISABLED";
    FD1S3IX cnt_n_174__i2 (.D(n69_adj_268[2]), .CK(clk_N_161), .CD(n221), 
            .Q(cnt_n[2])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174__i2.GSR = "DISABLED";
    FD1S3IX cnt_n_174__i1 (.D(n69_adj_268[1]), .CK(clk_N_161), .CD(n221), 
            .Q(cnt_n[1])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174__i1.GSR = "DISABLED";
    FD1S3IX cnt_p_175__i15 (.D(n69[15]), .CK(clk_in_c), .CD(n218), .Q(cnt_p[15])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175__i15.GSR = "DISABLED";
    LUT4 i8_4_lut_adj_10 (.A(n15), .B(cnt_n[13]), .C(n14), .D(cnt_n[8]), 
         .Z(n1704)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(74[13:25])
    defparam i8_4_lut_adj_10.init = 16'hfffe;
    FD1S3IX cnt_p_175__i14 (.D(n69[14]), .CK(clk_in_c), .CD(n218), .Q(cnt_p[14])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175__i14.GSR = "DISABLED";
    FD1S3IX cnt_p_175__i13 (.D(n69[13]), .CK(clk_in_c), .CD(n218), .Q(cnt_p[13])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175__i13.GSR = "DISABLED";
    FD1S3IX cnt_p_175__i12 (.D(n69[12]), .CK(clk_in_c), .CD(n218), .Q(cnt_p[12])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175__i12.GSR = "DISABLED";
    FD1S3IX cnt_p_175__i11 (.D(n69[11]), .CK(clk_in_c), .CD(n218), .Q(cnt_p[11])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175__i11.GSR = "DISABLED";
    FD1S3IX cnt_p_175__i10 (.D(n69[10]), .CK(clk_in_c), .CD(n218), .Q(cnt_p[10])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175__i10.GSR = "DISABLED";
    FD1S3IX cnt_p_175__i9 (.D(n69[9]), .CK(clk_in_c), .CD(n218), .Q(cnt_p[9])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175__i9.GSR = "DISABLED";
    FD1S3IX cnt_p_175__i8 (.D(n69[8]), .CK(clk_in_c), .CD(n218), .Q(cnt_p[8])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175__i8.GSR = "DISABLED";
    FD1S3IX cnt_p_175__i7 (.D(n69[7]), .CK(clk_in_c), .CD(n218), .Q(cnt_p[7])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175__i7.GSR = "DISABLED";
    FD1S3IX cnt_p_175__i6 (.D(n69[6]), .CK(clk_in_c), .CD(n218), .Q(cnt_p[6])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175__i6.GSR = "DISABLED";
    FD1S3IX cnt_p_175__i5 (.D(n69[5]), .CK(clk_in_c), .CD(n218), .Q(cnt_p[5])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175__i5.GSR = "DISABLED";
    FD1S3IX cnt_p_175__i4 (.D(n69[4]), .CK(clk_in_c), .CD(n218), .Q(cnt_p[4])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175__i4.GSR = "DISABLED";
    FD1S3IX cnt_p_175__i3 (.D(n69[3]), .CK(clk_in_c), .CD(n218), .Q(cnt_p[3])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175__i3.GSR = "DISABLED";
    FD1S3IX cnt_p_175__i2 (.D(n69[2]), .CK(clk_in_c), .CD(n218), .Q(cnt_p[2])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175__i2.GSR = "DISABLED";
    FD1S3IX cnt_p_175__i1 (.D(n69[1]), .CK(clk_in_c), .CD(n218), .Q(cnt_p[1])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(67[16:23])
    defparam cnt_p_175__i1.GSR = "DISABLED";
    CCU2D cnt_n_174_add_4_11 (.A0(cnt_n[9]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[10]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n1506), .COUT(n1507), .S0(n69_adj_268[9]), 
          .S1(n69_adj_268[10]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174_add_4_11.INIT0 = 16'hfaaa;
    defparam cnt_n_174_add_4_11.INIT1 = 16'hfaaa;
    defparam cnt_n_174_add_4_11.INJECT1_0 = "NO";
    defparam cnt_n_174_add_4_11.INJECT1_1 = "NO";
    CCU2D cnt_n_174_add_4_9 (.A0(cnt_n[7]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1505), .COUT(n1506), .S0(n69_adj_268[7]), .S1(n69_adj_268[8]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174_add_4_9.INIT0 = 16'hfaaa;
    defparam cnt_n_174_add_4_9.INIT1 = 16'hfaaa;
    defparam cnt_n_174_add_4_9.INJECT1_0 = "NO";
    defparam cnt_n_174_add_4_9.INJECT1_1 = "NO";
    LUT4 i5_3_lut_adj_11 (.A(cnt_p[12]), .B(cnt_p[10]), .C(cnt_p[11]), 
         .Z(n14_adj_252)) /* synthesis lut_function=(A+(B+(C))) */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(65[13:25])
    defparam i5_3_lut_adj_11.init = 16'hfefe;
    LUT4 i1475_4_lut (.A(n1707), .B(rst_n_in_c), .C(n10), .D(n1753), 
         .Z(n218)) /* synthesis lut_function=(!(A (B)+!A (B (C+!(D))))) */ ;
    defparam i1475_4_lut.init = 16'h3733;
    CCU2D cnt_n_174_add_4_7 (.A0(cnt_n[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1504), .COUT(n1505), .S0(n69_adj_268[5]), .S1(n69_adj_268[6]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174_add_4_7.INIT0 = 16'hfaaa;
    defparam cnt_n_174_add_4_7.INIT1 = 16'hfaaa;
    defparam cnt_n_174_add_4_7.INJECT1_0 = "NO";
    defparam cnt_n_174_add_4_7.INJECT1_1 = "NO";
    LUT4 i1_4_lut_adj_12 (.A(cnt_n[4]), .B(n1706), .C(cnt_n[5]), .D(n4), 
         .Z(clk_n_N_200)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(74[13:25])
    defparam i1_4_lut_adj_12.init = 16'hfcec;
    LUT4 i4_4_lut (.A(cnt_p[0]), .B(cnt_p[4]), .C(cnt_p[2]), .D(cnt_p[5]), 
         .Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(65[13:25])
    defparam i4_4_lut.init = 16'hfffe;
    LUT4 i1448_3_lut (.A(cnt_p[1]), .B(cnt_p[6]), .C(cnt_p[3]), .Z(n1753)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i1448_3_lut.init = 16'h8080;
    CCU2D cnt_n_174_add_4_5 (.A0(cnt_n[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1503), .COUT(n1504), .S0(n69_adj_268[3]), .S1(n69_adj_268[4]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174_add_4_5.INIT0 = 16'hfaaa;
    defparam cnt_n_174_add_4_5.INIT1 = 16'hfaaa;
    defparam cnt_n_174_add_4_5.INJECT1_0 = "NO";
    defparam cnt_n_174_add_4_5.INJECT1_1 = "NO";
    CCU2D cnt_n_174_add_4_3 (.A0(cnt_n[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1502), .COUT(n1503), .S0(n69_adj_268[1]), .S1(n69_adj_268[2]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174_add_4_3.INIT0 = 16'hfaaa;
    defparam cnt_n_174_add_4_3.INIT1 = 16'hfaaa;
    defparam cnt_n_174_add_4_3.INJECT1_0 = "NO";
    defparam cnt_n_174_add_4_3.INJECT1_1 = "NO";
    CCU2D cnt_n_174_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt_n[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .COUT(n1502), .S1(n69_adj_268[0]));   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(76[16:23])
    defparam cnt_n_174_add_4_1.INIT0 = 16'hF000;
    defparam cnt_n_174_add_4_1.INIT1 = 16'h0555;
    defparam cnt_n_174_add_4_1.INJECT1_0 = "NO";
    defparam cnt_n_174_add_4_1.INJECT1_1 = "NO";
    LUT4 i1470_4_lut (.A(n7), .B(rst_n_in_c), .C(n1524), .D(n8), .Z(n221)) /* synthesis lut_function=(!(A (B)+!A (B ((D)+!C)))) */ ;
    defparam i1470_4_lut.init = 16'h3373;
    LUT4 i2_2_lut (.A(cnt_n[4]), .B(cnt_n[5]), .Z(n7)) /* synthesis lut_function=(A+(B)) */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(74[13:25])
    defparam i2_2_lut.init = 16'heeee;
    LUT4 i2_3_lut (.A(cnt_n[6]), .B(cnt_n[3]), .C(cnt_n[1]), .Z(n1524)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i2_3_lut.init = 16'h8080;
    LUT4 i1_2_lut_adj_13 (.A(cnt_n[6]), .B(n1704), .Z(n1706)) /* synthesis lut_function=(A+(B)) */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(74[13:25])
    defparam i1_2_lut_adj_13.init = 16'heeee;
    LUT4 i3_3_lut (.A(n1704), .B(cnt_n[0]), .C(cnt_n[2]), .Z(n8)) /* synthesis lut_function=(A+(B+(C))) */ ;   // d:/git/oschina/step_mxo2/labs/src/divide_pwm.v(74[13:25])
    defparam i3_3_lut.init = 16'hfefe;
    
endmodule
//
// Verilog Description of module Debounce
//

module Debounce (clk_in_c, key_menu_c, menu_state_c_2, GND_net, clk_in_c_enable_8) /* synthesis syn_module_defined=1 */ ;
    input clk_in_c;
    input key_menu_c;
    output menu_state_c_2;
    input GND_net;
    output clk_in_c_enable_8;
    
    wire clk_in_c /* synthesis SET_AS_NETWORK=clk_in_c, is_clock=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(3[11:17])
    
    wire low_sw_r, low_sw, clk_in_c_enable_2;
    wire [18:0]cnt;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(18[12:15])
    
    wire n14, key_state_N_242, key_rst, key_an;
    wire [18:0]n81;
    
    wire n1492, n1491, n1490, n1565, n12, n8, n1489, n1488, 
        n1487, n1486, n1485, n1484, n22, n18, n20;
    
    FD1S3AY low_sw_r_34 (.D(low_sw), .CK(clk_in_c), .Q(low_sw_r)) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=10, LSE_RCOL=2, LSE_LLINE=37, LSE_RLINE=44 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(36[11:30])
    defparam low_sw_r_34.GSR = "ENABLED";
    FD1P3AY low_sw_33 (.D(key_menu_c), .SP(clk_in_c_enable_2), .CK(clk_in_c), 
            .Q(low_sw));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[7] 30[25])
    defparam low_sw_33.GSR = "ENABLED";
    LUT4 i2_2_lut (.A(cnt[7]), .B(cnt[11]), .Z(n14)) /* synthesis lut_function=(A+(B)) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i2_2_lut.init = 16'heeee;
    FD1S3AY key_state_35 (.D(key_state_N_242), .CK(clk_in_c), .Q(menu_state_c_2)) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=10, LSE_RCOL=2, LSE_LLINE=37, LSE_RLINE=44 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(45[10] 46[30])
    defparam key_state_35.GSR = "ENABLED";
    FD1S3AY key_rst_31 (.D(key_menu_c), .CK(clk_in_c), .Q(key_rst)) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=10, LSE_RCOL=2, LSE_LLINE=37, LSE_RLINE=44 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(13[11:27])
    defparam key_rst_31.GSR = "ENABLED";
    FD1S3IX cnt_176__i0 (.D(n81[0]), .CK(clk_in_c), .CD(key_an), .Q(cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i0.GSR = "ENABLED";
    LUT4 key_state_I_0_3_lut (.A(menu_state_c_2), .B(low_sw_r), .C(low_sw), 
         .Z(key_state_N_242)) /* synthesis lut_function=(A ((C)+!B)+!A !((C)+!B)) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(46[7:30])
    defparam key_state_I_0_3_lut.init = 16'ha6a6;
    CCU2D cnt_176_add_4_19 (.A0(cnt[17]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[18]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1492), .S0(n81[17]), .S1(n81[18]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176_add_4_19.INIT0 = 16'hfaaa;
    defparam cnt_176_add_4_19.INIT1 = 16'hfaaa;
    defparam cnt_176_add_4_19.INJECT1_0 = "NO";
    defparam cnt_176_add_4_19.INJECT1_1 = "NO";
    CCU2D cnt_176_add_4_17 (.A0(cnt[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[16]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1491), .COUT(n1492), .S0(n81[15]), .S1(n81[16]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176_add_4_17.INIT0 = 16'hfaaa;
    defparam cnt_176_add_4_17.INIT1 = 16'hfaaa;
    defparam cnt_176_add_4_17.INJECT1_0 = "NO";
    defparam cnt_176_add_4_17.INJECT1_1 = "NO";
    CCU2D cnt_176_add_4_15 (.A0(cnt[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1490), .COUT(n1491), .S0(n81[13]), .S1(n81[14]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176_add_4_15.INIT0 = 16'hfaaa;
    defparam cnt_176_add_4_15.INIT1 = 16'hfaaa;
    defparam cnt_176_add_4_15.INJECT1_0 = "NO";
    defparam cnt_176_add_4_15.INJECT1_1 = "NO";
    LUT4 i1479_4_lut (.A(n1565), .B(cnt[8]), .C(n12), .D(n8), .Z(clk_in_c_enable_2)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i1479_4_lut.init = 16'h4000;
    CCU2D cnt_176_add_4_13 (.A0(cnt[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1489), .COUT(n1490), .S0(n81[11]), .S1(n81[12]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176_add_4_13.INIT0 = 16'hfaaa;
    defparam cnt_176_add_4_13.INIT1 = 16'hfaaa;
    defparam cnt_176_add_4_13.INJECT1_0 = "NO";
    defparam cnt_176_add_4_13.INJECT1_1 = "NO";
    CCU2D cnt_176_add_4_11 (.A0(cnt[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1488), 
          .COUT(n1489), .S0(n81[9]), .S1(n81[10]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176_add_4_11.INIT0 = 16'hfaaa;
    defparam cnt_176_add_4_11.INIT1 = 16'hfaaa;
    defparam cnt_176_add_4_11.INJECT1_0 = "NO";
    defparam cnt_176_add_4_11.INJECT1_1 = "NO";
    CCU2D cnt_176_add_4_9 (.A0(cnt[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1487), 
          .COUT(n1488), .S0(n81[7]), .S1(n81[8]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176_add_4_9.INIT0 = 16'hfaaa;
    defparam cnt_176_add_4_9.INIT1 = 16'hfaaa;
    defparam cnt_176_add_4_9.INJECT1_0 = "NO";
    defparam cnt_176_add_4_9.INJECT1_1 = "NO";
    CCU2D cnt_176_add_4_7 (.A0(cnt[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1486), 
          .COUT(n1487), .S0(n81[5]), .S1(n81[6]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176_add_4_7.INIT0 = 16'hfaaa;
    defparam cnt_176_add_4_7.INIT1 = 16'hfaaa;
    defparam cnt_176_add_4_7.INJECT1_0 = "NO";
    defparam cnt_176_add_4_7.INJECT1_1 = "NO";
    CCU2D cnt_176_add_4_5 (.A0(cnt[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1485), 
          .COUT(n1486), .S0(n81[3]), .S1(n81[4]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176_add_4_5.INIT0 = 16'hfaaa;
    defparam cnt_176_add_4_5.INIT1 = 16'hfaaa;
    defparam cnt_176_add_4_5.INJECT1_0 = "NO";
    defparam cnt_176_add_4_5.INJECT1_1 = "NO";
    CCU2D cnt_176_add_4_3 (.A0(cnt[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1484), 
          .COUT(n1485), .S0(n81[1]), .S1(n81[2]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176_add_4_3.INIT0 = 16'hfaaa;
    defparam cnt_176_add_4_3.INIT1 = 16'hfaaa;
    defparam cnt_176_add_4_3.INJECT1_0 = "NO";
    defparam cnt_176_add_4_3.INJECT1_1 = "NO";
    LUT4 i11_4_lut (.A(cnt[10]), .B(n22), .C(n18), .D(cnt[14]), .Z(n1565)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i11_4_lut.init = 16'hfffe;
    LUT4 i5_4_lut (.A(cnt[5]), .B(cnt[17]), .C(cnt[13]), .D(cnt[16]), 
         .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i5_4_lut.init = 16'h8000;
    LUT4 i1_2_lut (.A(cnt[18]), .B(cnt[15]), .Z(n8)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut.init = 16'h8888;
    LUT4 i569_1_lut (.A(menu_state_c_2), .Z(clk_in_c_enable_8)) /* synthesis lut_function=(!(A)) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(45[10] 46[30])
    defparam i569_1_lut.init = 16'h5555;
    LUT4 i10_4_lut (.A(cnt[12]), .B(n20), .C(n14), .D(cnt[4]), .Z(n22)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i10_4_lut.init = 16'hfffe;
    CCU2D cnt_176_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n1484), 
          .S1(n81[0]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176_add_4_1.INIT0 = 16'hF000;
    defparam cnt_176_add_4_1.INIT1 = 16'h0555;
    defparam cnt_176_add_4_1.INJECT1_0 = "NO";
    defparam cnt_176_add_4_1.INJECT1_1 = "NO";
    LUT4 key_rst_I_0_2_lut (.A(key_rst), .B(key_menu_c), .Z(key_an)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(16[16:32])
    defparam key_rst_I_0_2_lut.init = 16'h6666;
    FD1S3IX cnt_176__i18 (.D(n81[18]), .CK(clk_in_c), .CD(key_an), .Q(cnt[18])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i18.GSR = "ENABLED";
    FD1S3IX cnt_176__i17 (.D(n81[17]), .CK(clk_in_c), .CD(key_an), .Q(cnt[17])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i17.GSR = "ENABLED";
    FD1S3IX cnt_176__i16 (.D(n81[16]), .CK(clk_in_c), .CD(key_an), .Q(cnt[16])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i16.GSR = "ENABLED";
    FD1S3IX cnt_176__i15 (.D(n81[15]), .CK(clk_in_c), .CD(key_an), .Q(cnt[15])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i15.GSR = "ENABLED";
    FD1S3IX cnt_176__i14 (.D(n81[14]), .CK(clk_in_c), .CD(key_an), .Q(cnt[14])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i14.GSR = "ENABLED";
    FD1S3IX cnt_176__i13 (.D(n81[13]), .CK(clk_in_c), .CD(key_an), .Q(cnt[13])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i13.GSR = "ENABLED";
    FD1S3IX cnt_176__i12 (.D(n81[12]), .CK(clk_in_c), .CD(key_an), .Q(cnt[12])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i12.GSR = "ENABLED";
    FD1S3IX cnt_176__i11 (.D(n81[11]), .CK(clk_in_c), .CD(key_an), .Q(cnt[11])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i11.GSR = "ENABLED";
    FD1S3IX cnt_176__i10 (.D(n81[10]), .CK(clk_in_c), .CD(key_an), .Q(cnt[10])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i10.GSR = "ENABLED";
    FD1S3IX cnt_176__i9 (.D(n81[9]), .CK(clk_in_c), .CD(key_an), .Q(cnt[9])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i9.GSR = "ENABLED";
    FD1S3IX cnt_176__i8 (.D(n81[8]), .CK(clk_in_c), .CD(key_an), .Q(cnt[8])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i8.GSR = "ENABLED";
    FD1S3IX cnt_176__i7 (.D(n81[7]), .CK(clk_in_c), .CD(key_an), .Q(cnt[7])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i7.GSR = "ENABLED";
    FD1S3IX cnt_176__i6 (.D(n81[6]), .CK(clk_in_c), .CD(key_an), .Q(cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i6.GSR = "ENABLED";
    FD1S3IX cnt_176__i5 (.D(n81[5]), .CK(clk_in_c), .CD(key_an), .Q(cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i5.GSR = "ENABLED";
    FD1S3IX cnt_176__i4 (.D(n81[4]), .CK(clk_in_c), .CD(key_an), .Q(cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i4.GSR = "ENABLED";
    FD1S3IX cnt_176__i3 (.D(n81[3]), .CK(clk_in_c), .CD(key_an), .Q(cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i3.GSR = "ENABLED";
    FD1S3IX cnt_176__i2 (.D(n81[2]), .CK(clk_in_c), .CD(key_an), .Q(cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i2.GSR = "ENABLED";
    FD1S3IX cnt_176__i1 (.D(n81[1]), .CK(clk_in_c), .CD(key_an), .Q(cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_176__i1.GSR = "ENABLED";
    LUT4 i6_2_lut (.A(cnt[9]), .B(cnt[3]), .Z(n18)) /* synthesis lut_function=(A+(B)) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i6_2_lut.init = 16'heeee;
    LUT4 i8_4_lut (.A(cnt[1]), .B(cnt[0]), .C(cnt[2]), .D(cnt[6]), .Z(n20)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i8_4_lut.init = 16'hfffe;
    
endmodule
//
// Verilog Description of module Debounce_U0
//

module Debounce_U0 (clk_in_c, key_up_c, GND_net, n49, n50, \cycle[0] , 
            n6, \cycle[2] , n13) /* synthesis syn_module_defined=1 */ ;
    input clk_in_c;
    input key_up_c;
    input GND_net;
    input n49;
    output n50;
    input \cycle[0] ;
    input n6;
    input \cycle[2] ;
    output n13;
    
    wire clk_in_c /* synthesis SET_AS_NETWORK=clk_in_c, is_clock=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/pulse_gen.v(3[11:17])
    wire [18:0]cnt;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(18[12:15])
    
    wire key_an;
    wire [18:0]n81;
    
    wire key_rst, low_sw, clk_in_c_enable_3, n1737, n23, n24, low_sw_r, 
        n1751, n14, n1472, n22, n1897, n16, n1471, n1470, n1469, 
        n1468, n1467, n1466, n1465, n1464;
    
    FD1S3IX cnt_177__i0 (.D(n81[0]), .CK(clk_in_c), .CD(key_an), .Q(cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i0.GSR = "ENABLED";
    LUT4 key_rst_I_0_2_lut (.A(key_rst), .B(key_up_c), .Z(key_an)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(16[16:32])
    defparam key_rst_I_0_2_lut.init = 16'h6666;
    FD1P3AY low_sw_33 (.D(key_up_c), .SP(clk_in_c_enable_3), .CK(clk_in_c), 
            .Q(low_sw));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[7] 30[25])
    defparam low_sw_33.GSR = "ENABLED";
    LUT4 i1432_2_lut (.A(cnt[18]), .B(cnt[17]), .Z(n1737)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1432_2_lut.init = 16'h8888;
    LUT4 i1481_4_lut (.A(n23), .B(cnt[13]), .C(n24), .D(cnt[8]), .Z(clk_in_c_enable_3)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i1481_4_lut.init = 16'h0400;
    FD1S3AY low_sw_r_34 (.D(low_sw), .CK(clk_in_c), .Q(low_sw_r)) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=10, LSE_RCOL=2, LSE_LLINE=46, LSE_RLINE=53 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(36[11:30])
    defparam low_sw_r_34.GSR = "ENABLED";
    FD1S3AY key_rst_31 (.D(key_up_c), .CK(clk_in_c), .Q(key_rst)) /* synthesis LSE_LINE_FILE_ID=6, LSE_LCOL=10, LSE_RCOL=2, LSE_LLINE=46, LSE_RLINE=53 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(13[11:27])
    defparam key_rst_31.GSR = "ENABLED";
    LUT4 i10_4_lut (.A(cnt[9]), .B(n1751), .C(cnt[14]), .D(n14), .Z(n23)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i10_4_lut.init = 16'hfffb;
    CCU2D cnt_177_add_4_19 (.A0(cnt[17]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[18]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1472), .S0(n81[17]), .S1(n81[18]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177_add_4_19.INIT0 = 16'hfaaa;
    defparam cnt_177_add_4_19.INIT1 = 16'hfaaa;
    defparam cnt_177_add_4_19.INJECT1_0 = "NO";
    defparam cnt_177_add_4_19.INJECT1_1 = "NO";
    LUT4 i9_4_lut (.A(cnt[0]), .B(cnt[1]), .C(cnt[12]), .D(cnt[2]), 
         .Z(n22)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i9_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut_rep_14 (.A(low_sw_r), .B(low_sw), .Z(n1897)) /* synthesis lut_function=(!((B)+!A)) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(40[19:40])
    defparam i1_2_lut_rep_14.init = 16'h2222;
    LUT4 i1_2_lut_3_lut (.A(low_sw_r), .B(low_sw), .C(n49), .Z(n50)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(40[19:40])
    defparam i1_2_lut_3_lut.init = 16'h2020;
    LUT4 i3_2_lut (.A(cnt[10]), .B(cnt[4]), .Z(n16)) /* synthesis lut_function=(A+(B)) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i3_2_lut.init = 16'heeee;
    LUT4 i11_4_lut (.A(cnt[3]), .B(n22), .C(n16), .D(cnt[6]), .Z(n24)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i11_4_lut.init = 16'hfffe;
    CCU2D cnt_177_add_4_17 (.A0(cnt[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[16]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1471), .COUT(n1472), .S0(n81[15]), .S1(n81[16]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177_add_4_17.INIT0 = 16'hfaaa;
    defparam cnt_177_add_4_17.INIT1 = 16'hfaaa;
    defparam cnt_177_add_4_17.INJECT1_0 = "NO";
    defparam cnt_177_add_4_17.INJECT1_1 = "NO";
    LUT4 i1446_4_lut (.A(cnt[15]), .B(cnt[5]), .C(cnt[16]), .D(n1737), 
         .Z(n1751)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i1446_4_lut.init = 16'h8000;
    LUT4 i1_2_lut (.A(cnt[11]), .B(cnt[7]), .Z(n14)) /* synthesis lut_function=(A+(B)) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(29[11:28])
    defparam i1_2_lut.init = 16'heeee;
    CCU2D cnt_177_add_4_15 (.A0(cnt[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1470), .COUT(n1471), .S0(n81[13]), .S1(n81[14]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177_add_4_15.INIT0 = 16'hfaaa;
    defparam cnt_177_add_4_15.INIT1 = 16'hfaaa;
    defparam cnt_177_add_4_15.INJECT1_0 = "NO";
    defparam cnt_177_add_4_15.INJECT1_1 = "NO";
    CCU2D cnt_177_add_4_13 (.A0(cnt[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n1469), .COUT(n1470), .S0(n81[11]), .S1(n81[12]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177_add_4_13.INIT0 = 16'hfaaa;
    defparam cnt_177_add_4_13.INIT1 = 16'hfaaa;
    defparam cnt_177_add_4_13.INJECT1_0 = "NO";
    defparam cnt_177_add_4_13.INJECT1_1 = "NO";
    CCU2D cnt_177_add_4_11 (.A0(cnt[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1468), 
          .COUT(n1469), .S0(n81[9]), .S1(n81[10]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177_add_4_11.INIT0 = 16'hfaaa;
    defparam cnt_177_add_4_11.INIT1 = 16'hfaaa;
    defparam cnt_177_add_4_11.INJECT1_0 = "NO";
    defparam cnt_177_add_4_11.INJECT1_1 = "NO";
    CCU2D cnt_177_add_4_9 (.A0(cnt[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1467), 
          .COUT(n1468), .S0(n81[7]), .S1(n81[8]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177_add_4_9.INIT0 = 16'hfaaa;
    defparam cnt_177_add_4_9.INIT1 = 16'hfaaa;
    defparam cnt_177_add_4_9.INJECT1_0 = "NO";
    defparam cnt_177_add_4_9.INJECT1_1 = "NO";
    CCU2D cnt_177_add_4_7 (.A0(cnt[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1466), 
          .COUT(n1467), .S0(n81[5]), .S1(n81[6]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177_add_4_7.INIT0 = 16'hfaaa;
    defparam cnt_177_add_4_7.INIT1 = 16'hfaaa;
    defparam cnt_177_add_4_7.INJECT1_0 = "NO";
    defparam cnt_177_add_4_7.INJECT1_1 = "NO";
    CCU2D cnt_177_add_4_5 (.A0(cnt[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1465), 
          .COUT(n1466), .S0(n81[3]), .S1(n81[4]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177_add_4_5.INIT0 = 16'hfaaa;
    defparam cnt_177_add_4_5.INIT1 = 16'hfaaa;
    defparam cnt_177_add_4_5.INJECT1_0 = "NO";
    defparam cnt_177_add_4_5.INJECT1_1 = "NO";
    LUT4 i1_4_lut (.A(\cycle[0] ), .B(n1897), .C(n6), .D(\cycle[2] ), 
         .Z(n13)) /* synthesis lut_function=(!(A ((C (D))+!B)+!A !(B))) */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(40[19:40])
    defparam i1_4_lut.init = 16'h4ccc;
    FD1S3IX cnt_177__i18 (.D(n81[18]), .CK(clk_in_c), .CD(key_an), .Q(cnt[18])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i18.GSR = "ENABLED";
    CCU2D cnt_177_add_4_3 (.A0(cnt[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1464), 
          .COUT(n1465), .S0(n81[1]), .S1(n81[2]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177_add_4_3.INIT0 = 16'hfaaa;
    defparam cnt_177_add_4_3.INIT1 = 16'hfaaa;
    defparam cnt_177_add_4_3.INJECT1_0 = "NO";
    defparam cnt_177_add_4_3.INJECT1_1 = "NO";
    CCU2D cnt_177_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n1464), 
          .S1(n81[0]));   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177_add_4_1.INIT0 = 16'hF000;
    defparam cnt_177_add_4_1.INIT1 = 16'h0555;
    defparam cnt_177_add_4_1.INJECT1_0 = "NO";
    defparam cnt_177_add_4_1.INJECT1_1 = "NO";
    FD1S3IX cnt_177__i17 (.D(n81[17]), .CK(clk_in_c), .CD(key_an), .Q(cnt[17])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i17.GSR = "ENABLED";
    FD1S3IX cnt_177__i16 (.D(n81[16]), .CK(clk_in_c), .CD(key_an), .Q(cnt[16])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i16.GSR = "ENABLED";
    FD1S3IX cnt_177__i15 (.D(n81[15]), .CK(clk_in_c), .CD(key_an), .Q(cnt[15])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i15.GSR = "ENABLED";
    FD1S3IX cnt_177__i14 (.D(n81[14]), .CK(clk_in_c), .CD(key_an), .Q(cnt[14])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i14.GSR = "ENABLED";
    FD1S3IX cnt_177__i13 (.D(n81[13]), .CK(clk_in_c), .CD(key_an), .Q(cnt[13])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i13.GSR = "ENABLED";
    FD1S3IX cnt_177__i12 (.D(n81[12]), .CK(clk_in_c), .CD(key_an), .Q(cnt[12])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i12.GSR = "ENABLED";
    FD1S3IX cnt_177__i11 (.D(n81[11]), .CK(clk_in_c), .CD(key_an), .Q(cnt[11])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i11.GSR = "ENABLED";
    FD1S3IX cnt_177__i10 (.D(n81[10]), .CK(clk_in_c), .CD(key_an), .Q(cnt[10])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i10.GSR = "ENABLED";
    FD1S3IX cnt_177__i9 (.D(n81[9]), .CK(clk_in_c), .CD(key_an), .Q(cnt[9])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i9.GSR = "ENABLED";
    FD1S3IX cnt_177__i8 (.D(n81[8]), .CK(clk_in_c), .CD(key_an), .Q(cnt[8])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i8.GSR = "ENABLED";
    FD1S3IX cnt_177__i7 (.D(n81[7]), .CK(clk_in_c), .CD(key_an), .Q(cnt[7])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i7.GSR = "ENABLED";
    FD1S3IX cnt_177__i6 (.D(n81[6]), .CK(clk_in_c), .CD(key_an), .Q(cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i6.GSR = "ENABLED";
    FD1S3IX cnt_177__i5 (.D(n81[5]), .CK(clk_in_c), .CD(key_an), .Q(cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i5.GSR = "ENABLED";
    FD1S3IX cnt_177__i4 (.D(n81[4]), .CK(clk_in_c), .CD(key_an), .Q(cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i4.GSR = "ENABLED";
    FD1S3IX cnt_177__i3 (.D(n81[3]), .CK(clk_in_c), .CD(key_an), .Q(cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i3.GSR = "ENABLED";
    FD1S3IX cnt_177__i2 (.D(n81[2]), .CK(clk_in_c), .CD(key_an), .Q(cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i2.GSR = "ENABLED";
    FD1S3IX cnt_177__i1 (.D(n81[1]), .CK(clk_in_c), .CD(key_an), .Q(cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/debouncekey.v(23[17:27])
    defparam cnt_177__i1.GSR = "ENABLED";
    
endmodule
